SBC81613 Socket 370 All-in-One CPU Card Series User
’
s Manual
BIOS Configuration
50
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Onchip sound
The SBC81613 support AC97 audio.
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CPU-To-PCI Write Buffer
When it was enabled, the CPU can write up to four dwords
of data to the PCI write buffer before the CPU must wait for
the PCI bus cycles to finish. When it was disabled, the CPU
must wait after each write cycle until the PCI bus signals
that it is ready to receive more data.
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PCI Dynamic Bursting
When it was enabled, every write transaction goes to the
write buffer. Burstable transactions then burst on the PCI
bus and nonburstable transactions do not
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PCI Master 0 WS Write
When Enabled, writes to the PCI bus are executed with zero
wait states.
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PCI Delayed Transaction
The chipset has an embedded 32-bit Firewallted write buffer
to support delay transactions cycles. Select Enabled to
support compliance with PCI specification version 2.1.
