AW86225
October 2021 V1.9
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PCB Layout Consideration
To obtain the optimal performance, PCB layout should be considered carefully. The suggested Layout is
illustrated in the following diagram:
`
B1
C4
B2
C5
VIA
PAD
Top layer
Second layer
HDP
HDN
VDD
TRIG/
INTN
GND
C1
C2
C3
GND
SCL
SDA
VREG
HDN
HDP
GND
GND
RSTN
GND
Figure 28 AW86225 Board Layout
Here are some guidelines:
1. Place the components around the chip as close as possible. The C1
、
C2 and C3 capacitors are
recommended to be X5R or X7R ceramic capacitors with a withstand voltage of 10V or more; the output
is recommended to reserve a combination of beads and capacitors to prevent EMI problems. The default
bead is 0
Ω, and the capacitor is not connecting.
2. The power supply flows through C2 and C3 to the VDD pin of the chip. It is recommended that VDD
separate power supply trace, the trace should be as short and thick as possible to ensure that current
flow of the trace capability is not less than 2A.
3. It is recommended that the VREG pin be directly connected to the main GND. The shorter the trace, the
better.
4. The GND of the chip and PCB board should be connected together on the surface layer or on the
second layer through VIA and then connected to the main GND.
5. The traces from HDP and HDN to the load should be as short and thick as possible, and the current flow
capacity of the traces not be less than 1.2A
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