AW86225
October 2021 V1.9
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10 Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
Detailed Functional Description
Power On Reset
The device provides a power-on reset feature that is controlled by LDO_OK. The reset signal will be generated
to perform a power-on reset operation, which will reset all circuits and configuration registers. When the VDD
power on, the VREG voltage raises and produce the LDO_OK indication, the reset is over.
Operation Mode
The device supports 3 operation modes.
Table 1 Operating Mode
Mode
Condition
Description
Power-Down
VDD = 0V or RSTN = 0V
Power supply is not ready or RSTN is tie to low.
Whole chip shutdown including I
2
C interface.
Standby
VDD > 2.7V
and RSTN = HIGH
and no wave is going
Power supply is ready and RSTN is tie to high.
Most parts of the device are power down for low power
consumption except I
2
C interface and LDO.
Active
Playing a waveform
Most parts of the device are working
Power supply OK
(V
VDD
> 2.7V)
And RSTN = 1
Power-down
Standby
Active
Power supply not ready
(V
VDD
= 0) or RSTN = 0
Start a play request
Waveform is over
or set a softrstn
Power supply not ready
(V
VDD
= 0) or RSTN = 0
Figure 11 Device operating modes transition
POWER-DOWN MODE
The device switches to power-down mode when the supply voltage is not ready or RSTN pin is set to low.
In this mode, all circuits inside this device will be shut down. I
2
C interface isn’t accessible in this mode, and all
of the internal configurable registers and Memory are cleared.
The device will jump out of the power-down mode automatically when the supply voltages are OK and RSTN
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