AW86225
October 2021 V1.9
www.awinic.com
34 Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
Bit
Symbol
R/W
Description
Default
7:0
VBAT
RO
The measured value of VDD in VBAT mode(high eight bits)
VDD=((VBAT*4+VBAT_LO)*6.1/1024)V
0
DET_LO: (Address 57h)
Bit
Symbol
R/W
Description
Default
7:6
Reserved
RO
Not used
0
5:4
VBAT_LO
RO
The measured value of VDD in VBAT mode(low two bits)
VDD=((VBAT*4+VBAT_LO)*6.1/1024)V
0
3:2
Reserved
RO
Not used
0
1:0
RL_LO
RO
the Measured value of resistance of LRA in DIAG mode(low two bits)
RL=((RL*4+RL_LO)*678)/(1024*d2s_gain)Ω
0
TRIMCFG3: (Address 5Ah)
Bit
Symbol
R/W
Description
Default
7:6
Reserved
RW
Not used
0
5:0
TRIM_LRA
RW
Register LRA trim setting
Trimming OSC frequency adaptive for LRA resonant frequency deviation, rate =
0.18%~0.26%
b000000: LRA(1+0%)(LRA real resonant frequency)
b000001~b011111: LRA(1+n*rate)
b111111~b100000: LRA(1-n*rate)
0
CHIPID: (Address 64h)
Bit
Symbol
R/W
Description
Default
7
Reserved
RO
Not used
1
6
CHIPID_H
RO
Enable I2C address selection pin
0: disable(AW86223/AW86224/AW86225)
1: enable(AW86214)
0
5:1
Reserved
RO
TRIM data
0
CHIPID_L
RO
Distinguish between 9pin chip and 12pin chip
0: 9pin chip(AW86224/AW86225)
1: 12pin chip(AW86223/AW86214)
0
ANACFG8: (Address 77h)
Bit
Symbol
R/W
Description
Default
7:6
TRTF_CTRL_HDRV
RW
HDP and HDN rising time control
b00: Trise = 60ns
b01: Trise = 20ns
b10: Trise = 16ns
b11: Trise = 4ns
0
5:0
Reserved
RW
Not used
0
awinic Confidential
