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Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners.

Avnet Electronics Marketing

9 of 33

Rev 1.0 04/17/2006

Released

Literature # ADS-005104

Configuration Mode

(M0 : M1 : M2)

Prom Clock En

JP24

Prom Enable

JP25

Mode Jumpers

JP2

Notes

Master Serial

DEFAULT

(0:0:0)

DEFAULT

FPGA provides CCLK

Master Parallel (Master SelectMAP)
(1:1:0)

FPGA provides CCLK

Slave Serial
(1:1:1)

PROM provides CCLK

Slave Parallel (Slave SelectMAP)
(0:1:1)

PROM provides CCLK

Table 5 – FPGA Configuration from PROM … Jumper Setting

Design Revisioning With Platform Flash

The Spartan-3 Development Board is designed to support the advanced features of the parallel Platform Flash PROM
including support for multiple design revisions and compressed configuration files. These features are disabled by the default
jumper settings. If an MCS (prom file) has been built with multiple revisions, use the “BIT SEL” jumper (JP3) to select the
desired revision. By default, no jumpers are installed and rev 0 will be loaded. To load revision 1, a jumper would be placed
at JP3 position 1-2.

2.2.3 Custom

Configuration

Methods

In addition to JTAG chain signals, J1 provides the user with an interface to the FPGA dedicated and dual function
programming pins. This enables fly-wire support for the programming methods mentioned above and gives flexibility for
developing a custom programming solution.

TD

I

TCK

TMS

TD

O

GN

D

GN

D

VCC

CS_B

D0

D2

D3

D1

DONE

PROG_B

INIT_

B

BUSY/DOUT

D4

D6

D7

D5

RD

WR

_B

CCLK

Figure 10 - Fly Wire Connection J1

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Summary of Contents for ADS-XLX-SP3-DEV1500

Page 1: ...e AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 1 of 33 Rev 1 0 04 17 2006 Released Literature ADS 005104 Xilinx Spartan 3 Development Kit User Guide ...

Page 2: ...O Connectors 28 2 16 Power 32 3 0 Software BSP 33 3 1 What is included 33 3 2 Hello World 33 3 3 On Chip Peripheral Bus OPB External Memory Project s 33 3 4 Web Server 33 Figures Figure 1 Spartan 3 Dev Top Side Figure 2 Spartan 3 Dev Bottom Side 4 Figure 3 Spartan 3 Development Board Picture 5 Figure 4 Spartan 3 Development Board Block Diagram 6 Figure 5 Boundary Scan Mode Selection via JP2 7 Figu...

Page 3: ...aracter LCD Pin out 15 Table 9 OLED Display Pin out 16 Table 10 OLED Display FPGA Pin out 17 Table 11 Video DAC FPGA Pin out 18 Table 12 Video DAC Jumpers 18 Table 13 Audio Codec FPGA Pin out 19 Table 14 Audio Codec Jumpers 19 Table 15 Dipswitch FPGA Pin out 20 Table 16 Pushbutton FPGA Pin out 20 Table 17 LED FPGA Pin out 21 Table 18 LVDS FPGA Pin out 22 Table 19 Timing Parameters for DDR SDRAM Pe...

Page 4: ...uate the features of the Spartan 3 but also to implement complete user applications Example projects are provided to help the user understand the design tool flow of the Xilinx Embedded Development Kit EDK software environment 1 2 Features FPGA Xilinx XC3S1500 2000 FG676 Spartan 3 FPGA I O Peripherals 2x16 character LCD 128x64 OSRAM OLED graphical display DB15 video DAC Audio CODEC PS2 keyboard mo...

Page 5: ...xternal Memory Project s o An OPB_DDR SDRAM memory project uses the MicroBlaze for accessing on board DDR SDRAM o An OPB_EMC project uses the MicroBlaze for accessing on board SRAM and Flash memory o Using the MicroBlaze soft processor execute code from internal Block RAM or external memory o Use the JTAG debug interface to download modified executable files to internal or external memories Ethern...

Page 6: ... One CLB Four Slices BlockRAM Dedicated Max Part Gates Cells Rows Col Total CLBs bits BRAM Multipliers DCMs User I O XC3S1500 1 5M 29 952 64 52 3 328 576K 32 32 4 XC3S2000 2M 46 080 80 64 5 120 720K 40 40 4 Table 2 Spartan 3 Attributes by Density 2 2 Configuration The Spartan 3 Development board supports Boundary scan as well as Master Slave Serial and Master Slave Parallel SelectMAP using the on ...

Page 7: ...n VCC 20 2 TDI 9 10 TDO 15 8 TMS 13 4 TCK 11 6 GND 19 21 1 3 5 7 9 11 or 13 Table 3 JTAG Headers Par 3 Par 4 Pin Out Figure 6 Configuration Debug Connections Par3 Parallel Cable IV MultiPro Ribbon J5 J5 is intended for connection to a 14 pin ribbon as supplied with a Xilinx Parallel Cable IV or MultiPro Desktop Tool Connect the ribbon cable to JP6 as shown below Note that the ribbon and connector ...

Page 8: ...e schematic carefully if you wish to change it JP7 JTAG Chain Selection Jumper Settings Pins 2 3 Standalone Mode Spartan 3 and XC18V04 PROMs Pins 1 2 and 4 5 Add AvBus P1 Connector to standalone Table 4 JTAG Chain Selection JP6 Figure 8 JTAG Chain Standalone Mode Default 2 2 2 Configuration With Platform Flash The Platform Flash PROM s provide easy to use non volatile storage for the configuration...

Page 9: ...e advanced features of the parallel Platform Flash PROM including support for multiple design revisions and compressed configuration files These features are disabled by the default jumper settings If an MCS prom file has been built with multiple revisions use the BIT SEL jumper JP3 to select the desired revision By default no jumpers are installed and rev 0 will be loaded To load revision 1 a jum...

Page 10: ...elects the configuration design when the PROM is programmed with multiple revisions When no jumpers are installed the PROM is set for external selection mode with revision 0 selected Installing jumpers on JP3 will pull the corresponding select pin high as indicated in the Figure below Default Uninstalled external enabled using Rev0 SEL0 SEL1 EN Figure 12 Design Revision Select JP4 HSWAP_EN Enables...

Page 11: ...nks 4 5 JP17 BANK 0 1 VCCO VOLTAGE VIO Selection selects the I O voltage for FPGA banks 0 and 1 Only one jumper should be placed at this connector Valid placements are 1 2 3 4 or 5 6 as indicated in the Figure below Default Installed across pins 1 2 3 3V supply Figure 14 I O Voltage Selection Banks 1 2 JP18 BANK 2 3 VCCO VOLTAGE VIO Selection selects the I O voltage for FPGA banks 2 and 3 Only one...

Page 12: ... the USB device to drive the configuration clock of the FPGA If using the USB device as the clock source disable the PROM by removing the jumper on JP25 and make sure the jumper settings on JP2 put the FPGA in a Slave configuration mode Default Open the FPGA or PROM provides the configuration clock JP28 USB RS232 RX This signal is intended to be an output from the FPGA to either the RX Input of th...

Page 13: ...r Jumpers Additional flexibility has been designed into the circuit in the form of resistor jumpers JTx and series resistors that can be moved or removed to alter the functionality of the board The purpose of some of these components may be discussed in other sections of this manual others may not be discussed at all The position of these components should not be altered without careful review of ...

Page 14: ...e 6 Available GCLK Sources There are clocks on the board which are included as reference for the Video DAC and Codec These are 25 175MHz and 24 576MHz respectively These were not brought in on GCLK inputs and are connected to the FPGA via bus switches JP20 must be present in order to use these clocks Single ended 25 175MHz Oscillator Header_IO 24 FPGA pin W21 Single ended 24 576MHz Oscillator Head...

Page 15: ...heir respective owners Avnet Electronics Marketing 15 of 33 Rev 1 0 04 17 2006 Released Literature ADS 005104 LCD Pin LCD Name FPGA pin RS DISP_RS P8 D0 DISP_D0 AE21 D1 DISP_D1 AF21 D2 DISP_D2 AE20 D3 DISP_D3 AF20 D4 DISP_D4 AE19 D5 DISP_D5 AE18 D6 DISP_D6 AE17 D7 DISP_D7 AD14 EN LCD_EN R8 Table 8 2x20 Character LCD Pin out ...

Page 16: ...Data Command HIGH Bus contains data for DDRAM LOW Bus contains command P8 5 R W WR I Read Write in 68 series mode Write strobe in 80 series mode Y7 6 E RD I E clock in 68 series mode Read strobe in 80 series mode Y10 7 D0 I O Data 0 AE21 8 D1 I O Data 1 AF21 9 D2 I O Data 2 AE20 10 D3 I O Data 3 AF20 11 D4 I O Data 4 AE19 12 D5 I O Data 5 AE18 13 D6 I O Data 6 AE17 14 D7 I O Data 7 AD14 15 VSSB I ...

Page 17: ...ht most significant bits of the DAV7125 RGB inputs with the two least significant bits of R G and B held at ground level Also provided by the FPGA to the ADV7125 are composite synchronization and blanking signals Vertical and horizontal synchronization signals are brought to pins 14 and 13 respectively of DB15 connector P4 but are not required The analog RGB signals generated by the ADV7123 are co...

Page 18: ...en 5 HDR_IO 13 E21 Green 6 HDR_IO 14 D21 Green 7 HDR_IO 15 F21 Blue 0 HDR_IO 16 E20 Blue 1 HDR_IO 17 B20 Blue 2 HDR_IO 18 F20 Blue 3 HDR_IO 19 D20 Blue 4 HDR_IO 20 F19 Blue 5 HDR_IO 21 B19 Blue 6 HDR_IO 22 G19 Blue 7 HDR_IO 23 C19 Video_clk HDR_IO 24 W21 Horiz_sync HDR_IO 25 W20 Vert_sync HDR_IO 26 Y21 Comp_sync HDR_IO 27 Y20 Blank HDR_IO 28 AC22 Table 11 Video DAC FPGA Pin out Note DAC signals ar...

Page 19: ...ive touch panel controller which may be used to provide digitally encoded position data to the FPGA via the AC97 interface X and Y touch screen inputs are provided to the UCB1400 via test points TP7 TP8 TP9 and TP10 An interrupt signal IRQ_OUT can be generated to the FPGA to indicate a touch panel entry was made 2 7 2 General Purpose I O A D Converter The UCB1400 CODEC provides ten general purpose...

Page 20: ...he bus switches by removing JP20 Removing JP20 will disconnect the PS2 connectors from the FPGA PS2 Mouse Keyboard protocol information may be found at http panda cs ndsu nodak edu achapwes PICmicro PS2 ps2 htm 2 9 Dip Push Button Switches An eight position dipswitch SPST has been installed on the board and attached to the FPGA These switches provide digital inputs to user logic as needed The sign...

Page 21: ...pairs These pairs labeled LVDS_P 0 29 and LVDS_N 0 29 are matched length Each pair _P and _N are routed as differential pairs and are tightly coupled Each pair may be used as transmit or receive and should be configured accordingly using termination resistors at the provided surface mount pads By default no termination resistors are installed A resistor should be added for each of the receive pair...

Page 22: ...DS_N18 95 3271 112 T22 LVDS_P19 95 80103 R137 45 P21 LVDS_N19 95 04219 44 P22 LVDS_P20 95 85368 R138 116 U23 LVDS_N20 95 19809 115 U24 LVDS_P21 95 96422 R139 48 T25 LVDS_N21 95 27415 47 T26 LVDS_P22 95 80083 R140 51 U25 LVDS_N22 95 09904 50 U26 LVDS_P23 95 86594 R141 122 W25 LVDS_N23 95 2591 121 W26 LVDS_P24 95 95932 R142 54 V24 LVDS_N24 95 03457 53 V25 LVDS_P25 95 93609 R143 125 R19 LVDS_N25 95 0...

Page 23: ...If a timing parameter is left out of the peripheral instantiation a default value is automatically used The Software BSP section of this manual has more information about setting up peripherals in EDK PLB DDRperipheral Timing Parameter Time ps or Number C_DDR_TMRD 12000 C_DDR_TWR 15000 C_DDR_TWTR 1 C_DDR_TRAS 70000 C_DDR_TRC 60000 C_DDR_TRFC 72000 C_DDR_TRCD 18000 C_DDR_TRRD 12000 C_DDR_TRP 18000 ...

Page 24: ...ransceiver is a 3222 available from Harris Intersil ICL3222CA and Analog Devices ADM3222 This transceiver is operating at 3 3V for VCC The FPGA transmit receive signals are connected to a 2 5V I O bank of the FPGA Bank 6 Because the 3222 minimum logic threshold high is 2V the 2 5V bank will work for this interface The internal charge pump creates the RS232 compatible output levels The standard RX ...

Page 25: ... Jumper Pin out These jumper pads provide the user with the ability to change the operating mode by moving the resistors By default the PHY is set to auto negotiate a link with a peer The available modes of operation are shown in the table below Operating Modes JT3 JT2 JT1 10BaseT Half Duplex Forced Mode 2 3 2 3 2 3 10BaseT Full Duplex Forced Mode 2 3 2 3 1 2 100Base TX Half Duplex Forced Mode 2 3...

Page 26: ...051 microcontroller This device supports full speed 12 Mbps and high speed 480 Mbps modes but does not support low speed mode 1 5 Mbps The FX2 interface to the Spartan 3 FPGA is a programmable state machine that supports 8 or 16 bit parallel data transfers This interface is called the General Programmable Interface GPIF The GPIF is controlled by Waveform Descriptors that are created with the Cypre...

Page 27: ...USB_FD12 V7 FD 13 USB_FD13 V5 FD 14 USB_FD14 V4 FD 15 USB_FD15 V3 Bidirectional FIFO data bus GPIFADR 0 USB_PC0 Optional FPGA_CCLK out see JT5 selection GPIFADR 1 FPGA_M2 SelectMAP port mode M2 GPIFADR 2 FPGA_M1 SelectMAP port mode M1 GPIFADR 3 FPGA_M0 SelectMAP port mode M0 GPIFADR 4 JTAG_TDI Optional JTAG interface TDI install RP96 GPIFADR 5 JTAG_TDO Optional JTAG interface TDO install RP96 GPIF...

Page 28: ... connector labeled P2 is directly connected to 93 I O of the Spartan 3 These signals labeled GEN_IO 0 32 LVDS_N 0 29 and LVDS_P 0 29 are connected to voltage selectable banks 2 and 3 of the FPGA Note that the signals labeled LVDS are routed as differential pairs This means that for example LVDS_N 0 is tightly coupled with LVDS_P 0 Consequently any LVDS signal left floating will experience cross ta...

Page 29: ...9 E11 AV_D5 AV_D7 H11 100 30 B10 AV_D6 AV_D8 C10 101 31 GND 3 3VDC 102 32 F11 AV_D9 AV_D11 G12 103 33 A11 AV_D10 AV_D12 B11 104 34 GND GND 105 35 E12 AV_D13 AV_D15 H12 106 36 D11 AV_D14 AV_D16 A12 107 37 5VDC GND 108 38 F12 AV_D17 AV_D19 F13 109 39 B12 AV_D18 AV_D20 C12 110 40 GND GND 111 41 D13 AV_D21 AV_D23 G13 112 42 B13 AV_D22 AV_D24 C13 113 43 GND 3 3VDC 114 44 E13 AV_D25 AV_D27 F14 115 45 E1...

Page 30: ... 29 K22 GEN_IO9 GEN_IO11 L22 100 30 L23 GEN_IO10 GEN_IO12 L21 101 31 GND 3 3VDC 102 32 M19 LVDS_N14 LVDS_N15 P20 103 33 M20 LVDS_P14 LVDS_P15 P19 104 34 GND GND 105 35 L20 GEN_IO13 GEN_IO15 M24 106 36 M26 GEN_IO14 GEN_IO16 L29 107 37 5VDC GND 108 38 N25 GEN_IO17 LVDS_N16 R22 109 39 N20 GEN_IO18 LVDS_P16 R21 110 40 GND GND 111 41 N23 LVDS_N17 LVDS_N18 T22 112 42 N24 LVDS_P17 LVDS_P18 T21 113 43 GND...

Page 31: ...11 B21 12 13 C21 HDR_IO12 HDR_IO13 E21 14 15 D21 HDR_IO14 HDR_IO15 F21 16 17 E20 HDR_IO16 HDR_IO17 B20 18 19 F20 HDR_IO18 HDR_IO19 D20 20 21 F19 HDR_IO20 HDR_IO21 B19 22 23 G19 HDR_IO22 HDR_IO23 C19 24 25 W21 HDR_IO24 HDR_IO25 W20 26 27 Y21 HDR_IO26 HDR_IO27 Y20 28 29 AC22 HDR_IO28 HDR_IO29 Y22 30 31 AD22 HDR_IO30 HDR_IO31 AB22 32 33 AB23 HDR_IO32 HDR_IO33 Y23 34 35 AD23 HDR_IO34 HDR_IO35 AA23 36 ...

Page 32: ...with center positive barrel connector The 5V is used as the input to a TI PT6944A which provides 3 3VDC and 1 2VDC Two National Semiconductor LP3966 ADJ parts provide 2 5V and 1 8V A separate DDR Termination Regulator National LP2995 is used to provide 1 25V reference and termination voltages A National LM2704 is used to provide 12V to the OLED display The barrel connector J7 is shown below in Fig...

Page 33: ...ynthesis and implementation over again To do this select Compile Program Sources and then Update Bitstream Finally just download the bit file to the board using the Download option 3 3 On Chip Peripheral Bus OPB External Memory Project s These are currently to be determined Likely projects will include DDR SDRAM Flash and SRAM 3 3 1 DDR SDRAM Project This example uses the On Chip Peripheral Bus OP...

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