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18 of 33
Rev 1.0 04/17/2006
Released
Literature # ADS-005104
Signal
*Header Equivalent
Net
FPGA pin#
Red(0) HDR_IO(0)
A19
Red(1) HDR_IO(1)
A22
Red(2) HDR_IO(2)
A20
Red(3) HDR_IO(3)
A23
Red(4) HDR_IO(4)
D19
Red(5) HDR_IO(5)
A21
Red(6) HDR_IO(6)
E19
Red(7) HDR_IO(7)
B23
Green(0) HDR_IO(8) B22
Green(1) HDR_IO(9) C23
Green(2) HDR_IO(10) C22
Green(3) HDR_IO(11) B21
Green(4) HDR_IO(12) C21
Green(5) HDR_IO(13) E21
Green(6) HDR_IO(14) D21
Green(7) HDR_IO(15) F21
Blue(0) HDR_IO(16)
E20
Blue(1) HDR_IO(17)
B20
Blue(2) HDR_IO(18) F20
Blue(3) HDR_IO(19)
D20
Blue(4) HDR_IO(20) F19
Blue(5) HDR_IO(21)
B19
Blue(6) HDR_IO(22)
G19
Blue(7) HDR_IO(23)
C19
Video_clk HDR_IO(24) W21
Horiz_sync HDR_IO(25) W20
Vert_sync HDR_IO(26) Y21
Comp_sync HDR_IO(27) Y20
Blank HDR_IO(28)
AC22
Table 11 – Video DAC - FPGA Pin-out
* Note: DAC signals are connected to the FPGA by way of a bus switch. This allows the re-use of header signals. If you wish to use
the 50-pin header J17, you may disable the bus switches using JP20.
Jumper
Function
Default
JP23
On – disables oscillator U28
OFF
JP20
On – enables bus switches
ON
JT10 Resistor
Jumper:
2-3 – Power save mode
1-2
Table 12 – Video DAC Jumpers