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Rev 1.0 04/17/2006
Released
Literature # ADS-005104
2.7 Audio
Codec
Manufacturer: Philips
Part #: UCB1400BE
A Philips UCB1400 stereo 20-bitAudio CODEC is used to provide stereo line-
level
and
monophonic microphone input and stereo line-level/headphone out functions for the Spartan-3 Development Board. 3.5mm audio jacks
provide input/output connectivity as follows:
J10: Stereo line-level out
J11: Stereo line-level in
J12: Mono microphone in
The FPGA communicates with the UCB1400 via an AC97 interface. The UCB operates in master mode; with the FPGA operating as
an AC97 controller device; in this mode the UCB1400 provides AC97 timing (Bit Clock). Details of the operation of the AC97 interface
are somewhat complex and beyond the scope of this document. Refer to the UCB1400 data sheet and the AC97 Specification Rev. 2.1
for further details.
A 24.576MHz clock is provided to the UCB1400. This clock is also connected to the FPGA and may be disabled by placing a shunt at
JP21.
2.7.1 Touch Panel Inputs
The UCB1400 includes a resistive touch panel controller which may be used to provide digitally encoded position data to the FPGA via
the AC97 interface. X and Y touch screen inputs are provided to the UCB1400 via test points TP7, TP8, TP9, and TP10. An interrupt
signal (IRQ_OUT) can be generated to the FPGA to indicate a touch panel entry was made.
2.7.2 General Purpose I/O & A/D Converter
The UCB1400 CODEC provides ten general-purpose I/O bits that may be set/read via the AC97 interface. Additionally, four analog
voltage inputs may be multiplexed into the UCB1400’s 10-bit A/D converter. The 10 GPIO bits are connected to Header J8 and the four
analog voltages are input via Header J9.
Signal
*Header Equivalent
Net
FPGA pin#
ac97_sdata_out HDR_IO(29)
Y22
ac97_sdata_in HDR_IO(30) AD22
ac97_bit_clk HDR_IO(31) AB22
ac97_sync_out HDR_IO(32)
AB23
ac97_reset_n HDR_IO(33)
Y23
irq_out HDR_IO(34)
AD23
adc_sync HDR_IO(35) AA23
clock_24_576M HDR_IO(36)
AE24
Table 13 – Audio Codec - FPGA Pin-out
* Note: Codec signals are connected to the FPGA by way of a bus switch. This allows the re-use of header signals. If you wish to use
the 50-pin header J17, you may disable the bus switches using JP20.
2.7.3 Codec Jumpers
Jumper
Function
Default
JP21
On – disables oscillator U26
OFF
JP20
On – enables bus switches
ON
JP22
On – Connects Reset to FPGA
Off – Forces Codec into reset
ON
Table 14 – Audio Codec Jumpers
Audio Codec
Mic
Line
In
Line
Out
Audio En
JP22
J10
J11
J12
J9
J8
