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Avnet Electronics Marketing
27 of 33
Rev 1.0 04/17/2006
Released
Literature # ADS-005104
FX2 Signal
FPGA net
FPGA pin
Description
CTL[0] USB_CTL0
AD2
CTL[1] USB_CTL1
AD1
CTL[2] USB_CTL2
AC2
Programmable control outputs
CTL[3]
CTL3_PROG#
Output enable for FPGA_PROG# driver
CTL[4]
FPGA_CS#
SelectMAP port chip select
CTL[5]
FPGA_RDWR#
SelectMAP port read/write enable
RDY[0] USB_RDY0
W3
RDY[1] USB_RDY1
W6
Sample-able ready inputs
RDY[2]
FPGA_BUSY
SelectMAP port busy indication
RDY[3]
FPGA_DONE
FPGA configuration DONE pin
RDY[4]
FPGA_INIT#
FPGA initialization pin
RDY[5]
USB_RDY5
Sample-able ready input connected to JP6:15
FD[0] USB_FD0
(D0)
Y15
FD[1] USB_FD1
(D1)
W14
FD[2] USB_FD2
(D2)
Y14
FD[3] USB_FD3
(D3)
AA14
FD[4] USB_FD4
(D4)
AC13
FD[5] USB_FD5
(D5)
AB13
FD[6] USB_FD6
(D6)
AB12
FD[7] USB_FD7
(D7)
AA12
Bidirectional FIFO data bus (also SMAP data)
FD[8] USB_FD8
W5
FD[9] USB_FD9
R5
FD[10] USB_FD10
U7
FD[11] USB_FD11 T4
FD[12] USB_FD12 V7
FD[13] USB_FD13 V5
FD[14] USB_FD14 V4
FD[15] USB_FD15 V3
Bidirectional FIFO data bus
GPIFADR[0]
USB_PC0
Optional FPGA_CCLK out – see JT5 selection
GPIFADR[1]
FPGA_M2
SelectMAP port mode - M2
GPIFADR[2]
FPGA_M1
SelectMAP port mode - M1
GPIFADR[3]
FPGA_M0
SelectMAP port mode - M0
GPIFADR[4]
JTAG_TDI
Optional JTAG interface – TDI (install RP96)
GPIFADR[5]
JTAG_TDO
Optional JTAG interface – TDO (install RP96)
GPIFADR[6]
JTAG_TMS
Optional JTAG interface – TMS (install RP96)
GPIFADR[7]
JTAG_TCK
Optional JTAG interface – TCK (install RP96)
GPIFADR[8]
USB_PE7
Address output connected to JP6:16
IFCLK USB_IFCLK
U5
Interface
clock, optional FPGA_CCLK (JT5)
PA0/INT0#
USB_INT0#
AC1
Port A I/O or active-low interrupt 0
PA1/INT1#
USB_INT1#
AB4
Port A I/O or active-low interrupt 1
PA2/SLOE
USB_SLOE
AB3
Port A I/O or slave-FIFO output enable
*PA3/WU2 *USB_WU2 *AA5
Port
A
I/O or alternate wake-up pin
PA4/FIFOADR0
USB_FA0
AA3
Port A I/O or slave-FIFO address select 0
PA5/FIFOADR1
USB_FA1
Y6
Port A I/O or slave-FIFO address select 1
PA6/PKTEND
USB_PEND
Y5
Port A I/O or slave-FIFO packet end
PA7/SLCS#
USB_SLCS#
Y4
Port A I/O or slave-FIFO enable
RESET#
RST#
R6
USB device active-low reset
Table 25 - USB Interface FPGA Pin-out
* Only connected on 3S2000 device. 1500 is a no-connect.