Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners.
Avnet Electronics Marketing
3 of 33
Rev 1.0 04/17/2006
Released
Literature # ADS-005104
Tables
Table 1: Ordering Information..................................................................................................................................................................... 5
Table 2 - Spartan-3 Attributes by Density................................................................................................................................................... 6
Table 3 - JTAG Headers (Par-3 & Par-4) Pin-Out ...................................................................................................................................... 7
Table 4 - JTAG Chain Selection "JP6" ....................................................................................................................................................... 8
Table 5 – FPGA Configuration from PROM … Jumper Setting .................................................................................................................. 9
Table 6 – Available GCLK Sources .......................................................................................................................................................... 14
Table 7 – Available Non-GCLK Osc. ........................................................................................................................................................ 14
Table 8 – 2x20 Character LCD Pin-out .................................................................................................................................................... 15
Table 9 - OLED Display Pin-out ............................................................................................................................................................... 16
Table 10 - OLED Display FPGA Pin-out................................................................................................................................................... 17
Table 11 – Video DAC - FPGA Pin-out .................................................................................................................................................... 18
Table 12 – Video DAC Jumpers ............................................................................................................................................................... 18
Table 13 – Audio Codec - FPGA Pin-out.................................................................................................................................................. 19
Table 14 – Audio Codec Jumpers ............................................................................................................................................................ 19
Table 15 - Dipswitch FPGA Pin-out .......................................................................................................................................................... 20
Table 16 - Pushbutton FPGA Pin-out ....................................................................................................................................................... 20
Table 17 - LED FPGA Pin-out .................................................................................................................................................................. 21
Table 18 - LVDS FPGA Pin-out................................................................................................................................................................ 22
Table 19 - Timing Parameters for DDR SDRAM Peripheral ..................................................................................................................... 23
Table 20 - RS232 FPGA Pin-out .............................................................................................................................................................. 24
Table 21 - RS232 Connector Pin-out ....................................................................................................................................................... 24
Table 22 - Ethernet PHY Modes............................................................................................................................................................... 25
Table 23 - Ethernet Jumpers and LEDs ................................................................................................................................................... 25
Table 24 - Ethernet FPGA Pin-out............................................................................................................................................................ 26
Table 25 - USB Interface FPGA Pin-out ................................................................................................................................................... 27
Table 26 - AvBus Connector "P1" Pin-out ................................................................................................................................................ 29
Table 27 - AvBus Connector "P2" Pin-out ................................................................................................................................................ 30
Table 28 - Header "JP1" Pin-out .............................................................................................................................................................. 31
