Automationdirect.com DL05, User Manual

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Standard
RLL
Instructions
5–56
Standard RLL Instructions
Accumulator Logic Instructions
K aaa
ANDD
The And Double is a 32 bit instruction that
logically ands the value in the
accumulator with two consecutive V
memory locations or an 8 digit (max.)
constant value (Aaaa). The result
resides in the accumulator. Discrete
status flags indicate if the result of the
And Double is zero or a negative number
(the most significant bit is on).
Operand Data Type DL05 Range
aaa
V memory V All (See page 4–28)
Pointer P All (See page 4–28)
Constant K 0–FFFFFFFF
Discrete Bit Flags Description
SP63 Will be on if the result in the accumulator is zero
SP70 Will be on is the result in the accumulator is negative
NOTE: The status flags are only valid until another instruction that uses the same
flags is executed.
In the following example, when X1 is on, the value in V2000 and V2001 will be loaded
into the accumulator using the Load Double instruction. The value in the
accumulator is anded with 36476A38 using the And double instruction. The value in
the accumulator is output to V2010 and V2011 using the Out Double instruction.
AND 36476A38
Handheld Programmer Keystrokes
LDD
V2000
X1
Load the value in V2000 and
V2001 into the accumulator
ANDD
K36476A38
AND the value in the
accumulator with
the constant value
36476A38
OUTD
V2010
Copy the value in the
accumulator to V2010 and
V2011
0 0 1 0 1 0 0 0 0 1 1 1 1 0 1 0
0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
V2000
2 8 7 A
0 0 0 1 0 1 0 0 0 1 0 0 0 1 1 0
0 1 0 1 0 1 0 0 0 1 1 1 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Acc.
Acc.
Acc.
V2010
2 8 3 8
V2001
5 4 7 E
V2011
1 4 4 6
0 1 0 1 0 1 0 0 0 1 1 1 1 1 1 0 0 0 1 0 1 0 0 0 0 1 1 1 1 0 1 0
0 1 1 0 1 0 1 0 0 0 1 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1
Direct SOFT
STR
$
SHFT
ANDST
L
3
D
SHFT
OUT
GX
3
D
SHFT
3
D
AND
V
SHFT
3
D
8
I
3
D
SHFT SHFT
JMP
K
0
A
3
D
6
G
4
E
7
H
6
G
ENT
1
B
ENT
2
C
0
A
1
B
0
A
ENT
2
C
0
A
0
A
ENT
0
A
And Double
(ANDD)