Atmel ATDH2200E, User Manual

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In-System Programming (ISP) Using Atmel’s ATDH2200E Configurator Programming System
3-6 ATDH2200E Programming Kit User Guide
1417E–CNFG–4/05
2. During programming, you will be asked to select the level that matches the
level seen on the A2 input pin of each target device.
3.5.4 Verifying the Device
against a *.BST File 1. Procedure
➞
Select “/V: Verify device against an Atmel file”.
2. Input File
➞
<design>.bst.
3. Options
➞
Default or previous settings are given. You may need to modify
the following:
– EEPROM Density
➞
Select the device density.
– FPGA Family
➞
Select “AT6K/Other”.
– A2 Bit Level
➞
Select the level that matches the level seen on the A2 pin of
the target device.
4. Press “Start Procedure”
(1)
.
3.5.5 Enabling the Clock
Output on the
AT17LV512A/
010A/020A/002A/
040A Configurator 1. Procedure
➞
Select “/M: Enable AT17LV512A/010A/020A/002A/040 Internal
Clock”.
2. Options
➞
Default or previous settings are given. You may need to modify
the following:
– EEPROM Density
➞
Select the device density.
– A2 Bit Level
➞
Select the level that matches the level seen on the A2 pin of
the target device.
3. Press “Start Procedure”
(1)(2)
.
3.5.6 Disabling the Clock
Output on the
AT17LV512A/
010A/020A/002A/
040A Configurator 1. Procedure
➞
Select “/M: Disable AT17LV512A/010A/020A/002A/040 Internal
Clock”.
2. Options
➞
Default or previous settings are given. You may need to modify
the following:
– EEPROM Density
➞
Select the device density.
– A2 Bit Level
➞
Select the level that matches the level seen on the A2 pin of
the target device.
3. Press “Start Procedure”
(1)(2)
.
Notes: 1. If CPS is being launched for the first time, the clock calibration dialog will
appear. Press “Yes” to proceed and select “High” for accurate calibration.
2. After the internal oscillator (DCLK) of the device is enabled/disabled, a
power cycle (reset) of the programming board is required before any other
programming procedure takes place.