Atmel ATA3741 Series, Operating

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9
4899B–RKE–10/06
ATA3741
When designing the system in terms of receiving bandwidth, the LO deviation must be consid-
ered as it also determines the IF center frequency. The total LO deviation is calculated to be the
sum of the deviation of the crystal and the XTO deviation of the ATA3741. Low-cost crystals are
specified to be within ±100 ppm. The XTO deviation of the ATA3741 is an additional deviation
due to the XTO circuit. This deviation is specified to be ±30 ppm. If a crystal of ±100 ppm is
used, the total deviation is ±130 ppm in that case. Note that the receiving bandwidth and the
IF-filter bandwidth are equivalent in ASK mode but not in FSK mode.
Figure 4-2. Receiving Frequency Response
5. Polling Circuit and Control Logic
The receiver is designed to consume less than 1 mA while being sensitive to signals from a cor-
responding transmitter. This is achieved via the polling circuit. This circuit enables the signal
path periodically for a short time. During this time the bit-check logic verifies the presence of a
valid transmitter signal. Only if a valid signal is detected does the receiver remain active and
transfer the data to the connected microcontroller. If there is no valid signal present, the receiver
is in sleep mode most of the time, resulting in low current consumption. This condition is called
polling mode. A connected microcontroller is disabled during that time.
All relevant parameters of the polling logic can be configured by the connected microcontroller.
This flexibility enables the user to meet the specifications in terms of current consumption, sys-
tem response time, data rate, etc.
Regarding the number of connection wires to the microcontroller, the receiver is very flexible. It
can be either operated by a single bi-directional line to save ports to the connected microcontrol-
ler, or it can be operated by up to three uni-directional ports.
5.1 Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the analog filtering is derived from one clock. As
seen in
Figure 5-1 on page 10 , this clock cycle T
Clk
is derived from the crystal oscillator (XTO) in
combination with a divider. The division factor is controlled by the logical state at pin MODE. The
frequency of the crystal oscillator (f
XTO
) is defined by the RF input signal (f
RFin
) which also
defines the operating frequency of the local oscillator (f
LO
) (See “RF Front End” on page 4 ).
-100.0
-90.0
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
-6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0
df (MHz)
dP (dB)
without SAW
with SAW