12
4899B–RKE–10/06
ATA3741
Figure 5-2.
Polling Mode Flow Chart
Figure 5-3.
Timing Diagram for a Completely Successful Bit Check
Bit-check
OK?
Sleep:
5-bit word defined by Sleep0 to Sleep4 in
OPMODE register
NO
YES
Sleep Mode:
All circuits for signal processing are
disabled. Only XTO and polling logic is
enabled.
Output level on pin IC_ACTIVE => low
I
S
= I
SON
T
Sleep
= Sleep
×
X
Sleep
×
1024
×
T
Clk
Start-up Mode:
The signal processing circuits are
enabled. After the start-up time (T
Startup
)
all circuits are in stable condition and
ready to receive.
I
S
= I
SON
T
Startup
Bit-check Mode:
The incoming data stream is analyzed.
If the timing indicates a valid transmitter
signal, the receiver is set to receiving
mode. Otherwise is set to Sleep mode.
I
S
= I
Son
T
Bitcheck
Receiving Mode:
The receiver is turned on permanently
and passes the data stream to the
connected microcontroller. It can be set
to Sleep mode through an OFF command
via pin DATA or ENABLE
I
S
= I
SON
OFF command
X
Sleep
:
Extension factor defined by X
SleepTemp
according to Table 5-7
T
Clk
:
Basic clock cycle defined by f
XTO
and pin
MODE
T
Startup
:
Is defined by the selected baud rate range
and T
Clk
. The baud rate range is defined
by Baud0 and Baud1 in the OPMODE
register.
T
Bitcheck
:
Depends on the result of the bit check.
If the bit check is ok, T
Bitcheck
depends
on the number of bits to be checked
(N
Bitchecked
) and on the utilized data rate.
If the bit check fails, the average time
period for that check depends on the
selected baud rate range on T
Clk
. The
baud rate range is defined by Baud0 and
Baud1 in the OPMODE register.
Bit check
Enable IC
DATA
1/2 Bit
Polling mode
Number of Checked Bits: 3
Bit check ok
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
Receiving mode
Dem_out
