Atmel ATA3741 Series, Operating

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13
4899B–RKE–10/06
ATA3741
5.3 Bit-check Mode
In bit-check mode, the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter and signals due to noise. This is done by subsequent time
frame checks where the distances between 2 signal edges are continuously compared to a pro-
grammable time window. The maximum count of this edge-to-edge test, before the receiver
switches to receiving mode, is also programmable.
5.3.1 Configuring the Bit Check
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks verify one
bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The maximum
count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable N
Bitcheck
in the OPMODE
register. This implies 0, 6, 12 and 18 edge-to-edge checks respectively. If N
Bitcheck
is set to a
higher value, the receiver is less likely to switch to the receiving mode due to noise. In the pres-
ence of a valid transmitter signal, the bit check takes less time if N
Bitcheck
is set to a lower value.
In polling mode, the bit-check time is not dependent on N
Bitcheck
. Figure 5-3 on page 12 shows an
example where 3 bits are tested successfully and the data signal is transferred to pin DATA.
Figure 5-4 shows how the time window for the bit check is defined by two separate time limits. If
the edge-to-edge time t
ee
is in between the lower bit check limit T
Lim_min
and the upper bit check
limit T
Lim_max
, the check will be continued. If t
ee
is smaller than T
Lim_min
or t
ee
exceeds T
Lim_max
,
the bit check will be terminated and the receiver will switch to sleep mode.
Figure 5-4. Valid Time Window for Bit Check
For best noise immunity it is recommended to use a low span between T
Lim_min
and T
Lim_max
.
This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A
“11111...” or a “10101...” sequence in Manchester or Bi-phase is a good choice in this regard. A
good compromise between receiver sensitivity and susceptibility to noise is a time window of
±25% regarding the expected edge-to-edge time t
ee
. Using preburst patterns that contain vari-
ous edge-to-edge time periods, the bit check limits must be programmed according to the
required span.
The bit-check limits are determined by means of the formula below:
T
Lim_min
= Lim_min
×
T
XClk
T
Lim_max
= (Lim_max –1)
×
T
XClk
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using the above formulas, Lim_min and Lim_max can be determined according to the required
T
Lim_min
, T
Lim_max
and T
XClk
. The time resolution when defining T
Lim_min
and T
Lim_max
is T
XClk
. The
minimum edge-to-edge time t
ee
(t
DATA_L_min
, t
DATA_H_min
) is defined in Section “Receiving Mode”
on page 15 . Due to this, the lower limit should be set to Lim_min
≥
10. The maximum value of
the upper limit is Lim_max = 63.
Dem_out
t
ee
T
lim_min
1/f
Sig
T
lim_max