Atmel ATA3741 Series, Operating

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4899B–RKE–10/06
ATA3741
5.3.2 Duration of the Bit Check
If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator
delivers random signals. The bit check is a statistical process and T
Bitcheck
varies for each check.
Therefore, an average value for T
Bitcheck
is given in “Electrical Characteristics”. T
Bitcheck
depends
on the selected baud rate range and on T
Clk
. A higher baud rate range causes a lower value for
T
Bitcheck
, resulting in lower current consumption in polling mode.
In the presence of a valid transmitter signal, T
Bitcheck
is dependent on the frequency of that sig-
nal, on f
Sig
, and on the count of the checked bits, N
Bitcheck
. A higher value for N
Bitcheck
thereby
results in a longer period for T
Bitcheck
, requiring a higher value for the transmitter preburst
T
Preburst
.
5.4 Receiving Mode
If the bit check is successful for all bits specified by N
Bitcheck
, the receiver switches to receiving
mode. As seen in Figure 5-3 on page 12 , the internal data signal is then switched to pin DATA. A
connected microcontroller can be woken up by the negative edge at pin DATA. The receiver
stays in that condition until it is explicitly switched back to polling mode.
5.4.1 Digital Signal Processing
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and
as a result converted into the output signal data. This processing depends on the selected baud
rate range (BR_Range).
Figure 5-8 illustrates how Dem_out is synchronized by the extended
clock cycle T
XClk
. This clock is also used for the bit-check counter. Data can change its state only
after T
XClk
elapsed. The edge-to-edge time period t
ee
of the Data signal, as a result, is always an
integral multiple of T
XClk
.
The minimum time period between two edges of the data signal is limited to t
ee
≥
T
DATA_min
. This
implies an efficient suppression of spikes at the DATA output. At the same time, it limits the max-
imum frequency of edges at DATA. This eases the interrupt handling of a connected
microcontroller. T
DATA_min
is to some extent affected by the preceding edge-to-edge time interval
t
ee
as illustrated in Figure 5-9 on page 16 . If t
ee
is in between the specified bit-check limits, the
following level is frozen for the time period T
DATA_min
= tmin1; if t
ee
is outside that bit check limit,
T
DATA_min
= tmin2 is the relevant stable time period.
The maximum time period for DATA to be low is limited to T
DATA_L_max
. This function ensures a
finite response time during programming or switching off the receiver via pin DATA. T
DATA_L_max
is thereby longer than the maximum time period indicated by the transmitter data stream. Figure
5-10 on page 16 gives an example where Dem_out remains low after the receiver has switched
to receiving mode.
Figure 5-8. Synchronization of the Demodulator Output
Clock bit check
counter
DATA
T
XClk
Dem_out
t
ee