Atmel ATA3741 Series, Operating

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16
4899B–RKE–10/06
ATA3741
Figure 5-9. Debouncing of the Demodulator Output
Figure 5-10. Steady L State Limited DATA Output Pattern after Transmission
After the end of a data transmission, the receiver remains active and random noise pulses
appear at pin DATA. The edge-to-edge time period t
ee
of the majority of these noise pulses is
equal to or slightly higher than T
DATA_min
.
5.4.2 Switching the Receiver Back to Sleep Mode
The receiver can be set back to polling mode via pin DATA or via pin ENABLE.
When using pin DATA, this pin must be pulled to low by the connected microcontroller for the
period t1.
Figure 5-11 on page 17 illustrates the timing of the OFF command (see also Figure
5-15 on page 22 ). The minimum value of t1 depends on the BR_Range. The maximum value for
t1 is not limited but it is recommended not to exceed the specified value to prevent erasing the
reset marker. This item is explained in more detail in Section
“Configuration of the Receiver” on
page 17 . Setting the receiver to sleep mode via DATA is achieved by programming bit 1 of the
OPMODE register to 1. Only one sync pulse (t3) is issued.
The duration of the OFF command is determined by the sum of t1, t2 and t10. After the OFF
command, the sleep time T
Sleep
elapses. Note that the capacitive load at pin DATA is limited.
The resulting time constant
τ
together with an optional external pull-up resistor may not be
exceeded to ensure proper operation.
If the receiver is set to polling mode via pin ENABLE, an “L” pulse (T
Doze
) must be issued at that
pin. Figure 5-12 on page 17 illustrates the timing of that command. After the positive edge of this
pulse, the sleep time T
Sleep
elapses. The receiver remains in sleep mode as long as ENABLE is
held to “L”. If the receiver is polled exclusively by a microcontroller, T
Sleep
can be programmed to
“0” to enable an instantaneous response time. This command is the faster option than via pin
DATA, but at the cost of an additional connection to the microcontroller.
DATA
tmin1
Lim_min
≤
CV_Lim < Lim_max
Dem_out
t
ee
tmin2
t
ee
CV_Lim < Lim_min or CV_Lim
≥
Lim_max
Bit check
Enable IC
DATA
Sleep mode Receiving mode
tmin2
Bit check mode
t
DATA_L_max
Dem_out