Atmel ATA3741 Series, Operating

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4899B–RKE–10/06
ATA3741
Figure 5-11. Timing Diagram of the OFF Command Via Pin DATA
Figure 5-12. Timing Diagram of the OFF Command Via Pin ENABLE
5.5 Configuration of the Receiver
The ATA3741 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT.
The registers can be programmed by means of the bi-directional DATA port. If the register con-
tents have changed due to a voltage drop, this condition is indicated by a certain output pattern
called reset marker (RM). The receiver must be reprogrammed in that case. After a power-on
reset (POR), the registers are set to default mode. If the receiver is operated in default mode,
there is no need to program the registers.
Table 5-2 on page 18 shows the structure of the registers. As shown in Table 5-1 , bit 1 defines if
the receiver is set back to polling mode via the OFF command, (see Section “Receiving Mode”
on page 15 ) or if it is programmed. Bit 2 represents the register address; it selects the appropri-
ate register to be programmed.
Out1 (microcontroller)
DATA (U3741BM)
Serial bi-directional
data line
X
Bit 1
("1")
(Start bit)
X
t1 t2 t3
t4
t5
t7
X
X
Startup mode
OFF command
Receiver
on
t10
T
Sleep
ENABLE
DATA (U3741BM)
Serial bi-directional
data line
X
X
X
T
Sleep
X
t
off
Receiver on Startup mode
T
Doze
Table 5-1. Effect of Bit 1 and Bit 2 in Programming the Registers
Bit 1 Bit 2 Action
1 x The receiver is set back to polling mode (OFF command)
0 1 The OPMODE register is programmed
0 0 The LIMIT register is programmed