Atmel ATA3741 Series, Operating

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4899B–RKE–10/06
ATA3741
3. RF Front End
The RF front end of the receiver is a heterodyne configuration that converts the input signal into
a 1-MHz IF signal. As seen in the block diagram, the front end consists of an LNA (low noise
amplifier), LO (local oscillator), a mixer, and an RF amplifier.
The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal
oscillator) generates the reference frequency f
XTO
. The VCO (voltage-controlled oscillator) gen-
erates the drive voltage frequency f
LO
for the mixer. f
LO
is dependent on the voltage at pin LF. f
LO
is divided by a factor of 64. The divided frequency is compared to f
XTO
by the phase frequency
detector. The current output of the phase frequency detector is connected to a passive loop filter
and thereby generates the control voltage V
LF
for the VCO. By means of that configuration, V
LF
is controlled in a way that f
LO
/ 64 is equal to f
XTO
. If f
LO
is determined, f
XTO
can be calculated
using the following formula:
The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. The
crystal should be connected to GND via a capacitor CL according to
Figure 3-1 . The value of the
capacitor is recommended by the crystal supplier. The value of CL should be optimized for the
individual board layout to achieve the exact value of f
XTO
and thereby of f
LO
. When designing the
system in terms of receiving bandwidth, the accuracy of the crystal and XTO must be
considered.
Figure 3-1. PLL Peripherals
The passive loop filter connected to pin LF is designed for a loop bandwidth of B
Loop
= 100 kHz.
This value for B
Loop
exhibits the best possible noise performance of the LO. Figure 3-1 shows
the appropriate loop filter components to achieve the desired loop bandwidth. If the filter compo-
nents are changed for any reason, please note that the maximum capacitive load at pin LF is
limited. If the capacitive load is exceeded, a bit check may no longer be possible since f
LO
can-
not settle before the bit check starts to evaluate the incoming data stream. Therefore, self polling
also will not work .
f
XTO
f
LO
64
-------- =
DVCC
XTO
LF
LFVCC
LFGND
V
S
C
L
C10
R1
C9
R1 = 820
Ω
C9 = 4.7 nF
C10 = 1 nF
V
S