10
4899B–RKE–10/06
ATA3741
Figure 5-1.
Generation of the Basic Clock Cycle
Pin MODE can now be set in accordance with the desired clock cycle T
Clk
. T
Clk
controls the fol-
lowing application-relevant parameters:
• Timing of the polling circuit including bit check
• Timing of analog and digital signal processing
• Timing of register programming
• Frequency of the reset marker
• IF filter center frequency (f
IF0
)
Most applications are dominated by two transmission frequencies: f
Send
= 315 MHz is mainly
used in the USA, f
Send
= 433.92 MHz in Europe. In order to ease the usage of all T
Clk
-dependent
parameters, the electrical characteristics display three conditions for each parameter.
• USA Applications
(f
XTO
= 4.90625 MHz, MODE = 0, T
Clk
= 2.0383 µs)
• Europe Applications
(f
XTO
= 6.76438 MHz, MODE = 1, T
Clk
= 2.0697 µs)
• Other applications
(T
Clk
is dependent on f
XTO
and on the logical state of pin MODE. The electrical characteristic
is given as a function of T
Clk
).
The clock cycle of some function blocks depends on the selected baud rate range (BR_Range)
which is defined in the OPMODE register. This clock cycle T
XClk
is defined by the following for-
mulas for further reference:
BR_Range =
BR_Range0:
T
XClk
= 8
×
T
Clk
BR_Range1:
T
XClk
= 4
×
T
Clk
BR_Range2:
T
XClk
= 2
×
T
Clk
BR_Range3:
T
XClk
= 1
×
T
Clk
DVCC
XTO
MODE
T
Clk
f
XTO
16
15
14
XTO
Divider
:14/:10
L : USA (:10)
H: Europe (:14)
