Publication No. 981050 REV. A
PXIe-1209 User Manual
Astronics Test Systems
Getting Started 4-1
Chapter 4
Operation
The PXIe-1209 is a register-based instrument that is controlled through a series of
I/O registers described in Chapter 6. The exact method of accessing and
addressing the I/O registers is dependent on the PXI carrier used to interface the
module to your data acquisition or test system. Refer to the carrier’s
documentation for information on the address mapping of a PXI’s I/O registers and
to your system software documentation for details on data access.
Programming
NOTE
: For most users, it is advisable to use either the LabWindows/CVI or the
LabVIEW driver in your application development environment to program the
PXIe-1209. Consult Chapter 5,
Software Operation
, of this manual for a
description of how to use the software drivers supplied with this module
Writing Register Values
Normal 16-bit wide register values can be written in one write operation using 32-
bit register access. However, some pulse parameters, such as the pulse period,
pulse width, and pulse delay, require more than 16-bits. Special attention must be
given when programming these values. To prevent a pulse parameter from
changing until the entire value is written, the order of the write operations is
important. The internal logic is configured to only accept the change when the
high-order bits are written. Therefore, the application software must write the low
bits first, then the middle bits, and lastly the high bits.
Pulse Programming
With the RUN bit disabled (0) in the Control/Status register, set the desired pulse
frequency, pulse width, pulse delays, high/low amplitude, desired trigger control
mode, pulse mode (single or double pulse), and run mode (single, continuous,
burst, or follow trigger). After setting the desired pulse parameters, a finite amount
of time (<20 ms) is required for configuration of the internal logic. The module will
signal that it is ready to run by setting the RDY bit. Application software should
verify the module is ready by reading the RDY bit. If desired, an interrupt can be
generated to signal this event. Once the RDY bit is verified, enable the RUN bit
(1). Modifications can be made to all settings except for RMODE without clearing
the RUN bit; however, the RDY bit will go low momentarily and there may be a
pulse glitch while the configuration is being adjusted.
Pulse Delay
The pulse delay is defined as the amount of time from the leading edge of Sync
Summary of Contents for PXIe-1209
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