Publication No. 981050 REV. A
PXIe-1209 User Manual
Astronics Test Systems
Identification and Configuration Registers 6-5
DDS Frequency - Low
PXIe-
1209
Reg.08
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Write
15
Low Order Bits
0
Read
15
Low Order Bits
0
DDS Frequency - High
PXIe-
1209
Reg.0A
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Write
31
High Order Bits
16
Read
31
High Order Bits
16
Notes:
1.
Each bit represents ~0.093Hz (use 400MHz
(2
32
– 1) for programming).
2.
When FGM = 1 (frequency divider mode), the frequency must be set to a value
25MHz and
50MHz.
3.
The registers must be written in the order low then high. The new frequency divider value
does not take effect until the high order register is written.
Frequency Divider – Low
PXIe-
1209
Reg.0C
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Write
15
Low Order Bits
0
Read
15
Low Order Bits
0
Frequency Divider – High
PXIe-
1209
Reg.0E
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Write FGM
-
29
High Order Bits
16
Read FGM
0
29
High Order Bits
16
FGM
Frequency Generation Mode (0 = DDS output directly controls the pulse
frequency (default), 1 = pulse frequency is controlled by a combination of the
DDS output and a divider value)
Notes:
1.
These registers are only used when the FGM bit the Frequency Mode Control register is set.
2.
The pulse frequency is equal to (DDS Frequency
4)
Frequency Divider value.
3.
The minimum divider value is two (2).
4.
The registers must be written in the order low then high. The new frequency divider value
does not take effect until the high order register is written.
Summary of Contents for PXIe-1209
Page 22: ......
