PXIe-1209 User Manual
Publication No. 981050 REV. A
Getting Started 4-2
Astronics Test Systems
Out to the leading edge of the output pulse. Pulse delay is user programmable
from 5 ns to 5 seconds.
Sync Out
Sync Out marks the beginning of a single or double pulse sequence. The time
from Sync Out to Pulse Out is user programmable from 5ns to 5 seconds. The
width of Sync Out is programmable as short (~5 ns) or long (~50 ns). The short
width should be used when pulsing at frequencies above 20 MHz. For frequencies
less than 20 MHz, the short or long width can be used.
In addition, when using external triggering, it is important to keep in mind the time
from external trigger to Sync Out time as specified in
Sync Out
in Chapter 1. This
time is due to intrinsic propagation delays of the input circuitry and pulse
generation logic. The time may vary from board to board, but will not vary
significantly for a particular board.
In burst mode and when using synchronous gating, the time from the external
trigger to Sync Out will jitter 5-10 ns from trigger to trigger, if the DDS/Divider
Mode (FGM = 1) is being used (see
Pulse and Timing Control Logic
in Chapter
1 for more details). This is due to the required synchronization of the
asynchronous external trigger to the internal clock on the PXIe-1209.
Synchronization is not required when producing a Single or Double pulse
sequence, so this jitter does not occur.
Frequency (Internal Pulse Repetition Rate)
The internal pulse repetition rate can be derived directly from the DDS output or
controlled by a combination of the DDS output and a divider value. The direct
DDS output should be used when producing continuous fixed frequency pulses,
software initiated pulse burst, or asynchronous gating operations. This method
allows the most flexible control and highest resolution of the frequency.
The combination of the DDS output and a divider value should be used when
doing externally triggered pulse burst or synchronous gating operations. When
using the divider, the DDS must be set to a frequency between 25 and 50 MHz.
This clock is multiplied by four internally to provide a 100 to 200 MHz base clock
for the input to the divider. The first pulse after an incoming external trigger or
gate signal will occur synchronous to this base clock, which varies in period from 5
to 10ns, depending on the x4 internal clock frequency. If the direct DDS output
were used, the pulse would be synchronous to that output clock, which may have
a much longer period than 10 ns.
Single Pulse vs. Double Pulse
The DP bit in the Control/Status Register selects whether a single pulse (or double
pulse) occurs when triggered. It is important to remember that the Double Pulse
Spacing is the time from the rising edge of the first pulse to the rising edge of the
second pulse; therefore, the Double Pulse Spacing must be set to a value greater
than the Pulse Width.
Summary of Contents for PXIe-1209
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