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63
*PSC {1|0}
Sets the power-on status clear bit. When set to 1 the Standard Event Enable register
and Status Byte Enable registers will be cleared when power is turned ON. 0 setting
indicates the Enable registers will be loaded with Enable register masks from non-
volatile memory at power ON.
*PSC?
Queries the power-on status clear setting. Returns 0 or 1.
*ESR?
Queries the Standard Event register. Returns the decimal value of the binary-
weighted sum of bits.
*ESE <
value
>
Standard Event enable register controls which bits will be logically OR’
d together to
generate the Event Summary bit 5 (ESB) within the Status Byte.
*ESE?
Queries the Standard Event enable register. Returns the decimal value of the binary-
weighted sum of bits.
*STB?
Read the Status Byte. Returns the decimal value of the binary-weighted sum of bits.
*SRE <
value
>
Service Request enable register controls which bits from the Status Byte should be
use to generate a service request when the bit value = 1.
*SRE?
Queries the Service Request enable register. Returns the decimal value of binary-
weighted sum of bits.
7.4.8. Status Reporting
Status reporting system is configured using two types of registers. An Event Register
and a Summary register. The summary register is known as the Status Byte register
and records high-level summary information acquired by the event registers.
An Event register reports defined conditions or messages at each bit. The bits are
latched and remain at an active state until the register is either Read or Cleared.
Reading the event register automatically clears the register and sets all bits to inactive
state or 0. When querying an event register the information is returned as a decimal
number representing the binary-weighted sum of all bits within the register.
