ASEM BM1 Series, User Manual

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36 SECTION 4 – System Start-U
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4.3.6.8 LPSS Configuration
BIOS setting Function Configuration options
LPSS configuration settings
LPSS I2C #1 Support (D22:F0) Enable / Disable LPSS I2C #1 Support [PCI Mode]
Set LPSS I2C #1 Speed Selecto LPSS I2C #1 Speed [Fast Mode]
LPSS I2C #2 Support (D22:F1) Enable / Disable LPSS I2C #2 Support [PCI Mode]
Set LPSS I2C #2 Speed Select LPSS I2C #2 Speed [Fast Mode]
LPSS SPI #1 Support (D25:F0) Enable / Disable LPSS SPI #1 Support [PCI Mode]
LPSS SPI #2 Support (D25:F1) Enable / Disable LPSS SPI #2 Support [PCI Mode]
LPSS SPI #3 Support (D25:F2) Enable / Disable LPSS SPI #3 Support [PCI Mode]
LPSS Clock Gating Configuration
LPSS I2C #1 Clock Gating Configuration Enable / Disable LPSS I2C #1 Clock Gating [Enable] [Disable]
LPSS I2C #2 Clock Gating Configuration Enable / Disable LPSS I2C #2 Clock Gating [Enable] [Disable]
LPSS SPI #1 Clock Gating Configuration Enable / Disable LPSS I2C #1 Clock Gating [Enable] [Disable]
LPSS SPI #2 Clock Gating Configuration Enable / Disable LPSS I2C #2 Clock Gating [Enable] [Disable]
LPSS SPI #3 Clock Gating Configuration Enable / Disable LPSS I2C #3 Clock Gating [Enable] [Disable]
Table 19 - LPSS Configuration
4.3.6.9 PCI Express configuration
BIOS setting Function Configuration options
PCI express configuration settings
PCI Express Clock Gating PCI Express clock gating Enable / disable for each root port [Enabled] [Disabled]
Port8xh Decode PCI Express Port8xh Decode [Enabled] [Disabled]
Peer memory Write Enable Peer memory Write Enable / Disable [Enabled] [Disabled]
Compliance Mode Compliance Mode Enable / Disable [Enabled] [Disabled]
PCI Express Root Port 1 Control the PCI Express Root Port. AUTO: To disable unused root port auto-
matically for the most optimum power savings. Enable: Enable PCIe root port
Disable: Disable PCIe root port
PCI Express Root Port 2 Control the PCI Express Root Port. AUTO: To disable unused root port auto-
matically for the most optimum power savings. Enable: Enable PCIe root port
Disable: Disable PCIe root port
PCI Express Root Port 5 Control the PCI Express Root Port. AUTO: To disable unused root port auto-
matically for the most optimum power savings. Enable: Enable PCIe root port
Disable: Disable PCIe root port
Table 20 - PCI Express Configuration
4.3.6.10 PCI Express Root Port 1
BIOS setting Function Configuration options
PCI Express Root Port 1
Control the PCI Express Root Port.
Auto: To disable unused root port automatically
for the most optimum power savings.
Enable: Enable PCIe root port
Disable: Disable PCIe root port
If DISABLED, goto ENABLE first then AUTO on next boot
ASPM
PCI Express Active State Power management Settings [Enabled] [Disabled]
L1 substates PCI Express L1 Substates settings [L1.1 & L1.2]
ACS Enable / Disable access control services extended capability [Enabled] [Disabled]
URR PCI express unsupported request reporting Enable/Disable [Enabled] [Disabled]
FER PCI express Device Fatal Error reporting Enable/Disable [Enabled] [Disabled]
NFER PCI express Device Non-Fatal Error reporting Enable/Disable [Enabled] [Disabled]
CER PCI express Device Correctable Error Reporting Enable/Disable [Enabled] [Disabled]
CTO PCI express Completion Timer T0 Enable/Disable [Enabled] [Disabled]
SEFE Root PCI express system err or on fatal error Enable / Disable [Enabled] [Disabled]
SENFE Root PCI express system error on Non-Fatal error Enable / Disable [Enabled] [Disabled]
SECE Root PCI express system error on Correctable Error Enable / Disable [Enabled] [Disabled]
PME SCI PCI Express PME SCI Enable / Disable [Enabled] [Disabled]
Hot Plug PCI Express Hot Plug Enable / Disable [Enabled] [Disabled]
PCIe Speed Configure PCIe Speed [Enabled] [Disabled]
Transmitter Half Swing Transmitter Half Swing Enable / Disable [Enabled] [Disabled]
Extra bus Reserved Extra bus Reserved for bridges behind this Root Bridge [0-7]
Reserved Memory Reserved memory and Prefetchable Memory Range for this Root Bridge [1-20MB]
Reserved I/O Reserved range for this Root Bridge [4K/8K/12K/16K/20K]
PCH PCIe LTR Configuration
PCH PCIE LTR PCH PCIE Latency Reporting [Enabled] [Disabled]
Snoop Latency Override
Snoop Latency Override for PCH PCIE
Disabled: Disable override.
Manual: Manually enter override values.
Auto (default): Maintain default BIOS flow
Non Snoop Latency Override
Non Snoop Latency Override for PCH PCIE
Disabled: Disable override.
Manual: Manually enter override values.
Auto (default): Maintain default BIOS flow
PCIE LTR Lock PCIE LTR Configuration Lock [Enabled] [Disabled]
PCIe Selectable De-emphasis When the link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an Up-
stream component.
1b-3,5 dB
0b-6 dB
[Enabled] [Disabled]
Table 21 - PCI Express Root Port 1
4.3.6.11 PCI Express Root Port 2
BIOS setting Function Configuration options
PCI Express Root Port 2
Control the PCI Express Root Port.
Auto: To disable unused root port automatically
for the most optimum power savings.
Enable: Enable PCIe root port
Disable: Disable PCIe root port