Artesyn ATCA-7475, Installation And Use Manual

Page: 183 / 282

Maps and Registers
ATCA-7475 Installation and Use (6806800S38D)
183
6.4.26 Telecom Clock Control and Supervision Registers
6.4.26.1 Telecom Clock Device Control/Status Registers
The on board telecom clock device ACS8225B is initialized via its SPI interface. The telecom
clock device state machine programs the device to deliver 25 MHz in its output lines.
The Service Processor can use the SPI access register to reprogram the device.
7 - Reserved 0 r
Table 6-53 Misc (Ethernet Link and CPU Error) Status Register (continued)
Address Offset: 0x57
Bit Signal Description Default Access
Table 6-54 ACS8225B SPI Access Register
Address Offset: 0x5C
Bit Description Default Access
6:0 ACS8825B SPI Address (max 128 bytes) CPU_PWROK: 0 LPC: r/w
7 SPI Command
0: Write ACS8525B Register:
Triggers 16 SPI clocks and shifts the address and
data out to MOSI.
1: Read ACS8525B Register:
Triggers 16 SPI clocks and shifts the address out to
MOSI. The Data on MISO is shifted in. CPU_PWROK: 0 LPC: r/w
Table 6-55 ACS8225B SPI Status Register
Address Offset: 0x5D
Bit Description Default Access
6:0 ACS8825B SPI Address (max 128 bytes) CPU_PWROK: 0 r