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Maps and Registers

ATCA-7475 Installation and Use (6806800S38D

)

172

6.4.12.2 PCA9555 Internal Register Access

For debug purpose, the internal virtual PCA9555 registers can be read by the IPMC and the 
Service Processor.

Table 6-37 Address Control for PCA9555 Internal Register

Address Offset: 
CPU0 Device1 (Slave address 0x20): 0x34
CPU0 Device2 (Slave address 0x21): 0x36
CPU1 Device1 (Slave address 0x20): 0x3C
CPU1 Device1 (Slave address 0x21): 0x3E

Bit

Description

Default

Acces
s

2:0

Internal PCA9555 register address

0

r/w

7:3

Reserved

0

r

Table 6-38 Content of PCA9555 Internal Register

Address Offset: 
CPU0 Device1 (Slave address 0x20): 0x35
CPU0 Device2 (Slave address 0x21): 0x37
CPU1 Device1 (Slave address 0x20): 0x3D
CPU1 Device1 (Slave address 0x21): 0x3F

Bit

Description

Default

Access

7:0

Content of PCA9555 register

0

r

Summary of Contents for ATCA-7475

Page 1: ...ATCA 7475 Installation and Use P N 6806800S38D May 2014 ...

Page 2: ...hanges from time to time in the content hereof without obligation of Artesyn to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to an Artesyn website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without ...

Page 3: ...and Inspecting the Blade 43 2 2 Environmental and Power Requirements 43 2 2 1 Environmental Requirements 44 2 2 2 Power Requirements 47 2 3 Blade Layout 50 2 4 Switch Settings 51 2 5 Installing the Blade Accessories 54 2 5 1 DIMM Memory Modules 54 2 5 2 MO297 SSD Module 56 2 5 3 Accelerator Module 58 2 6 Installing and Removing the Blade 59 2 6 1 Installing the Blade 59 2 6 2 Removing the Blade 62...

Page 4: ...on 82 4 2 2 Default Access Parameters 82 4 2 3 Connecting to the Blade 83 4 3 Changing Configuration Settings 83 4 4 Boot Options 85 4 4 1 Supported Boot Devices 85 4 4 2 Selecting the Boot Device 85 4 4 3 By Boot Menu 87 4 5 IPMI Boot Parameter 88 4 6 Restoring BIOS Default Settings 89 4 7 BIOS Setup Configuration 90 4 7 1 Main 90 4 7 2 Advanced 91 4 7 3 IPMI 96 4 7 4 Security 97 4 7 5 Boot 98 4 ...

Page 5: ... 3 8 Log Area Reset Cleared 113 4 11 3 9 System Boot 113 4 12 LED Usage 113 4 13 Upgrading the BIOS 113 4 14 BIOS Status Codes 114 5 Functional Description 121 5 1 Block Diagram 121 5 2 Processor 122 5 3 Memory 122 5 4 Platform Controller Hub PCH 123 5 4 1 PCH I O Controller Features 124 5 4 2 PCH Intel QuickAssist and Quad MAC PCIe Endpoint 125 5 5 Firmware Flashes 126 5 6 Ethernet Ports 127 5 6 ...

Page 6: ...vecreek PCH DH8900CC APIC D31 F0 Interrupt Mapping 141 6 1 3 NMI Generation 142 6 2 FPGA Registers 143 6 3 Registers 144 6 3 1 Register Decoding 145 6 3 1 1 LPC Decoding 145 6 3 1 2 SPI Register Decoding 146 6 3 2 POST Code Register 146 6 4 FPGA Register Mapping 148 6 4 1 LPC I O Register Map 148 6 4 2 IPMC SPI Register Map 148 6 4 3 Module Identification Register 151 6 4 4 Version Register 151 6 ...

Page 7: ...Status Register 169 6 4 12 PCI Express Hot Plug I2C IO Expander Registers 169 6 4 12 1 Hot Plug Virtual Pin Port Registers 170 6 4 12 2 PCA9555 Internal Register Access 172 6 4 13 Flash Status and Protection Registers 173 6 4 14 BIOS Boot Mode Register 175 6 4 15 Update Channel Equalization Control Register 175 6 4 16 IPMC E Keying Status Register 176 6 4 17 IPMC E Keying Control Register 177 6 4 ...

Page 8: ...1 1 Boot Bank Sensor 201 8 1 2 Fail Safe Logic 201 8 2 Glue Logic FPGA Flash Selection 204 9 Supported IPMI Commands 205 9 1 Standard IPMI Commands 205 9 1 1 Global IPMI Commands 205 9 1 2 System Interface Commands 205 9 1 3 Watchdog Commands 206 9 1 4 SEL Device Commands 207 9 1 5 FRU Inventory Commands 207 9 1 6 Sensor Device Commands 208 9 1 7 Chassis Device Commands 209 9 1 7 1 System Boot Opt...

Page 9: ...ommand 239 9 4 9 Set Handle Switch Command 240 9 4 10 Get Payload Communication Time Out Command 240 9 4 11 Set Payload Communication Time Out Command 241 9 4 12 Enable Payload Control Command 242 9 4 13 Disable Payload Control Command 242 9 4 14 Reset IPMC Command 243 9 4 15 Hang IPMC Command 243 9 4 16 Graceful Reset Command 244 9 4 17 Get Payload Shutdown Time Out Command 245 9 4 18 Set Payload...

Page 10: ...cedure 269 11 1 3 Interface 270 11 1 3 1 KCS Interface 270 11 1 3 2 IPMB 0 270 11 1 3 3 IPMI over LAN BASE 270 11 2 IPMC Upgrade 271 11 3 BIOS FPGA Upgrade 272 11 4 Upgrade Package 273 A Replacing the Battery 275 A 1 Replacing the Battery 275 B Related Documentation 279 B 1 Artesyn Embedded Technologies Embedded Computing Documentation 279 B 2 Manufacturers Documents 280 B 3 Related Specifications...

Page 11: ...on 92 Table 4 5 Advanced CPU Configuration Processor Power Management 92 Table 4 6 Advanced CPU Configuration System Agent SA Configuration 93 Table 4 7 Advanced CPU Configuration System Agent SA Configuration Intel R I O Acceleration Technology 93 Table 4 8 Advanced Memory Configuration 93 Table 4 9 Advanced USB Configuration 95 Table 4 10 Advanced SATA Configuration 95 Table 4 11 Advanced Super ...

Page 12: ...127 Table 5 2 Faceplate Serial Interfaces 132 Table 5 3 IPMC Debug Console Destination Selection 133 Table 5 4 Variants of the Intel DH8900CC PCH Device 135 Table 5 5 SMBus Interface 135 Table 5 6 SMBus Address Map 136 Table 6 1 Non APIC PIC mode 8259 Mode Interrupt Mapping 140 Table 6 2 APIC Mode Interrupt Mapping 141 Table 6 3 NMI Sources 142 Table 6 4 Register Default 144 Table 6 5 Register Acc...

Page 13: ...s 166 Table 6 34 Interrupt Mask and Map Registers 168 Table 6 35 Base Link Interrupt Status Register 169 Table 6 36 Hot Plug Virtual Pin Port Register 170 Table 6 37 Address Control for PCA9555 Internal Register 172 Table 6 38 Content of PCA9555 Internal Register 172 Table 6 39 Flash Status Register 173 Table 6 40 Default Boot SPI Flash Write Enable 174 Table 6 41 Recovery Boot SPI Flash Write Ena...

Page 14: ...HY Address Register 191 Table 6 69 MII Management Interface Control and Address Register 191 Table 6 70 MII Management Interface Lower Byte Register 192 Table 6 71 MII Management Interface Upper Byte Register 192 Table 6 72 IPMC BIOS Communication Register 1 193 Table 6 73 IPMC BIOS Communication Register 2 193 Table 6 74 IPMC BIOS Communication Register 3 193 Table 6 75 LPC Scratch Register 193 T...

Page 15: ... 29 IPMC Modes 231 Table 9 30 Get Status Command Description 231 Table 9 31 Get Serial Interface Properties Command Description 234 Table 9 32 Set Serial Interface Properties Command Description 235 Table 9 33 Get Debug Level Command Description 236 Table 9 34 Set Debug Level Command Description 237 Table 9 35 Get Hardware Address Command Description 238 Table 9 36 Set Hardware Address Command Des...

Page 16: ...U Information 251 Table 10 2 Artesyn ECC MAC Address Record 252 Table 10 3 ArtesynECC MAC Address Descriptor 252 Table 10 4 Interface Type Assignments 253 Table 10 5 Power Configuration 254 Table 10 6 IPMI Sensors Overview 254 Table 10 7 Sensor Data Records 260 Table 11 1 HPM Upgrade Package 273 Table B 1 Artesyn Embedded Technologies Embedded Computing Publications 279 Table B 2 Manufacturer s Do...

Page 17: ...Connector Pinout Rows A to D 76 Figure 3 12 P23 Backplane Connector Pinout Rows E to H 76 Figure 3 13 P30 Backplane Connector Pinout Rows A to D 77 Figure 3 14 P30 Backplane Connector Pinout Rows E to H 77 Figure 3 15 P31 Backplane Connector Pinout Rows A to D 78 Figure 3 16 P31 Backplane Connector Pinout Rows E to H 78 Figure 3 17 P32 Backplane Connector Pinout Rows A to D 79 Figure 3 18 P32 Back...

Page 18: ...ATCA 7475 Installation and Use 6806800S38D 18 List of Figures Figure 11 1 IPMC Component Elements 271 Figure 11 2 SPI Busses Connection 273 Figure A 1 Location of On board Battery 276 ...

Page 19: ...nts hardware accessories switch settings installation and removal procedures Controls Indicators and Connectors on page 65 describes external interfaces of the blade This includes connectors and LEDs BIOS on page 81 describes the features and setup of BIOS Functional Description on page 121 describes the functional blocks of the blade in detail This includes a block diagram description of the main...

Page 20: ...Advanced Telecommunications Computing Architecture BIOS Basic Input Output System CPU Central Processing Unit DDR Double Data Rate DIMM Dual Inline Memory Module ECC Error Correction Code EMC Electromagnetic Compatibility EMV Elektromagnetische Vertraeglichkeit EN European Norm ESD Electrostatic Sensitive Device FPGA Field Programmable Gate Array GND Ground IPMB Intelligent Platform Management Bus...

Page 21: ...Group PIM Power Input Module PMC PCI Mezzanine Card POST Power On Self Test PROM Programmable Read Only Memory RTC Real Time Clock RTM Rear Transition Module RoHS Restriction of the use of Certain Hazardous Substances SAS Serial Attached SCSI SATA Serial ATA SCSI Small Computer System Interface SDR Sensor Data Record SMI Serial Management Interface SOL Serial over LAN SPD Serial Presence Detect SP...

Page 22: ...on screenoutputandcoderelatedelements or commands in body text Courier Bold Used to characterize user input and to separate it from system output Reference Used for references and for table and figure descriptions File Exit Notation for selecting a submenu text Notation for variables and keys text Notation for software buttons to click on the screen and parameter description Repeated item for exam...

Page 23: ...tion Part Number Publication Date Description 6806800S38A September 2013 Initial Version 6806800S38B January 2014 Updated Table Environmental Requirements on page 45 added a new chapter Chapter 8 Boot Bank Selection updated the section Artesyn Embedded Technologies Specific Commands on page 223 and updated sections EMC on page 25 and EMV on page 30 6806800S38C January 2014 Updated Table Blade Vari...

Page 24: ...ATCA 7475 Installation and Use 6806800S38D About this Manual 24 About this Manual ...

Page 25: ...stry and industrial control Only personnel trained by Artesyn Embedded Technologies or persons qualified in electronics or electrical engineering are authorized to install remove or maintain the product The information given in this manual is meant to complete the knowledge of a specialist and must not be used as replacement for qualified personnel Keep away from live circuits inside the equipment...

Page 26: ...e The COM1 ETH1 ETH2 USB1 and USB2 interfaces are considered as debug maintenance ports During normal operation no cables must be connected to these ports Cables attached to these ports during maintenance must not exceed a length of 3m Installation Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life Before touching the b...

Page 27: ...nclosure according to the IEC EN UL CSA 60950 1 requirements All other devices that are connected only for service purposes to the VGA interface needs supervision during operation and must be disconnected after maintenance Blade Damage Blade surface High humidity and condensation on the blade surface causes short circuits Do not operate the blade outside the specified environmental limits Make sur...

Page 28: ... malfunction if their setting is changed Therefore do not change settings of switches marked as reserved The setting of switches which are not marked as reserved has to be checked and changed before blade installation Blade Damage Setting resetting the switches during operation can cause blade damage Therefore check and change switch settings before you install the blade Battery Blade Damage Wrong...

Page 29: ...tte an die für Sie zuständige Geschäftsstelle von Artesyn Embedded Technologies Das System erfüllt die für die Industrie geforderten Sicherheitsvorschriften und darf ausschließlich für Anwendungen in der Telekommunikationsindustrie und im Zusammenhang mit Industriesteuerungen verwendet werden Einbau Wartung und Betrieb dürfen nur von durch Artesyn Embedded Technologies ausgebildetem oder im Bereic...

Page 30: ...kann im Wohnbereich Funkstörungen verursachen In diesem Fall kann vom Betreiber verlangt werden angemessene Maßnahmen durchzuführen Die nachfolgend aufgeführten Schnittstellen sind Wartungsschnittstellen COM1 ETH1 ETH2 USB1 USB2 Während des Normalbetriebs darf an diesen Schnittstellen kein Kabel angeschlossen sein Im Wartungsfall angeschlossene Kabel dürfen eine Länge von 3m nicht überschreiten In...

Page 31: ...halb des Gebäudes haben Ein Primary Protector wie in GR 1089 CORE beschrieben ist keine ausreichende Absicherung um die Gebäude internen Schnittstellen mit Leitungen außerhalb des Gebäudes zu verbinden Betrieb Stellen Sie sicher daß Geräte die dauerhaft mit der VGA Schnittstelle verbunden sind über ein Brandschutzgehäuse verfügen die die Anforderungen der IEC EN UL CSA 60950 1 Norm erfüllen Alle a...

Page 32: ...verursachen In diesem Fall ist Leitung A immer noch unter Spannung auch wenn sie vom Versorgungskreislauf getrennt ist und umgekehrt Prüfen Sie deshalb immer ob die Leitung spannungsfrei ist bevor Sie Ihre Arbeit fortsetzen um Schäden oder Verletzungen zu vermeiden Schaltereinstellungen Fehlfunktion des Blades Schalter die mit Reserved gekennzeichnet sind können mit produktionsrelevanten Funktione...

Page 33: ...che Explosionen und Beschädigungen des Blades zur Folge haben Verwenden Sie deshalb nur den Batterietyp der auch bereits eingesetzt wurde und befolgen Sie die Installationsanleitung Umweltschutz Entsorgen Sie alte Batterien und oder Blades Systemkomponenten RTMs stets gemäß der in Ihrem Land gültigen Gesetzgebung und den Empfehlungen des Herstellers ...

Page 34: ...ATCA 7475 Installation and Use 6806800S38D Sicherheitshinweise 34 ...

Page 35: ...a total of 8 DIMM slots 4GB 8GB and 16GB DDR3 modules in VLP available Single slot ATCA form factor 280mm x 322mm Direct CPU to PCIe interface providing 40 PCIe Gen3 lanes 8 Gbps Next Generation Communications Platform from Intel codename Crystal Forest with onboard DH8900CC SKU1 Platform controller I O Hub PCH Additional two Next Generation Communications Platform PCH devices via ATCA 7470 Accele...

Page 36: ... predefined Artesyn Embedded Technologies system ISO 8601 Y2K compliance NEBS Standard GR 63 CORE1 ETSI EN 300019 series 1 The blade does not fulfill the Unpacked Equipment Shock Criteria as defined in NEBS GR63 4 3 2 During tests whichconsistedofdroppingthebladefrom100mmheight weobservedthatonsomebladestheAdvancedTCAzone 2 and 3 connectors got damaged Although it was possible to manually repair t...

Page 37: ...Introduction ATCA 7475 Installation and Use 6806800S38D 37 The following figure is the copy of Declaration of Conformity for ATCA 7475 Figure 1 1 Declaration of Conformity ...

Page 38: ...Logic Ground logic signal return have to be connected The connection may be implemented inside the shelf for example at the backplane or the shelf has to provide a possibility to lead Logic Ground out of the shelf for external connection to Central Office Ground For further information refer to Telcordia GR 1089 CORE section 9 8 2 requirement R9 14 The product has been designed to meet the directi...

Page 39: ...Identification The following figure shows the location of the serial number label 1 5 Ordering Information The ATCA 7475 is a high performance ATCA compliant single board computer designed for demanding storage and processing applications Figure 1 2 Serial Number Location ...

Page 40: ...Cache 256KB L2 Cache per core 32Kb 32KB L1 Cache per core 64 GB DDR3 1600 with 8x8GB DIMM pre installed ATCA 7475 128GB ATCA 7475 Blade with Dual Intel Xeon E5 2648L V2 10 Core 1 9GHz processors Ivy Bridge 70W TDP 2 5MB per Core Last Level Cache 256KB L2 Cache per core 32Kb 32KB L1 Cache per core 128 GB DDR3 1600 with 8x16GB DIMM pre installed ATCA 7475 0GB CE ATCA 7475 Blade with Dual Intel Xeon ...

Page 41: ...ation and Use 6806800S38D 41 ATCA 7XMMOD SATA2 64 GB SLC SLIM SATA MO 297 on board solid state disk module SA BBS WR43 7475 DVD BBS SW and WindRiver Linux 4 3 for ATCA 7475 Table 1 4 Blade Accessories continued Accessory Description ...

Page 42: ...Introduction ATCA 7475 Installation and Use 6806800S38D 42 ...

Page 43: ...h the blade and dispose of it according to your country s legislation 2 2 Environmental and Power Requirements In order to meet the environmental requirements the blade has to be tested in the system in which it is to be installed Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life Before touching the blade or electronic...

Page 44: ...es such as hard disks or PMC modules with more restrictive environmental requirements Operating temperatures refer to the temperature of the air circulating around the blade and not to the actual component temperature Blade Damage Blade Surface High humidity and condensation on the blade surface causes short circuits Do not operate the blade outside the specified environmental limits Make sure the...

Page 45: ...ssories Temp Change 0 25 C min according to Telcordia GR 63 CORE 0 25 C min Rel Humidity Normal Operation 5 rH to 85 rh non condensing Exceptional Operation 5 rH to 90 rh non condensing According to Telcordia GR 63 CORE NEBS andEN300019 1 3 Classes3 1 and 3 1E 5 to 95 non condensing according to Telcordia GR 63 CORE NEBS and EN 300 019 1 1 Classes 1 2 and 2 3 Vibration 1g from 5 to 200Hz and back ...

Page 46: ...re safety you have to make sure that the temperatures at the locations specified in the following are not exceeded If not stated otherwise the temperatures should be measured by placing a sensor exactly at the given locations Figure 2 1 Location of Critical Temperature Spots Blade Top Side Temperature Spot 2 on 48 DC DC Converter Max 100 C exact location in the geometric middle of the heat spreade...

Page 47: ... For information on the accessories power requirements refer to the documentation delivered together with the respective accessory or consult your local Artesyn Embedded Technologies representative for further details Table 2 2 Critical Temperature Limits Component Thermal Design Power Max Case or Junction Temperature All product variants except ATCA 7475 xGB CE Intel Xeon E5 2648L V2 70W Tj max 1...

Page 48: ...e 2 3 Power Requirements Characteristic Value Rated Voltage Exception in the US and Canada 48 VDC to 60 VDC 48 VDC Operating Voltage Exception in the US and Canada 39 VDC to 72 VDC 39 VDC to 60 VDC Max power consumption of ATCA 7475 with ATCA 7470 ACCEL MOD and with RTM ATCA 736x 10G including SAS HDD All product variants except ATCA 7475 xGB CE 250W typ 215W ATCA 7475 xGB CE variant 300W typ 265W...

Page 49: ...th software simultaneously exercising as many functions and interfaces as possible This includes a particular load software provided by Intel designed to stress the processors to reach their theoretical maximum power specification Any difference in the system configuration or the software executed by the processors may affect the actual power dissipation Depending on the actual operating configura...

Page 50: ...rdware Preparation and Installation ATCA 7475 Installation and Use 6806800S38D 50 2 3 Blade Layout The following figure shows the location of components on the ATCA 7475 Figure 2 2 ATCA 7475 Blade Layout ...

Page 51: ...FF in their default configuration Switch selection used only for debugging are grouped in separate devices which are not assembled in volume production Switches reside on the component side 1 and are not covered by any other component Their location is shown in the following figure Figure 2 3 Switch Location Bottom Side of the Blade ...

Page 52: ...OFF Reserved Table 2 5 Switch SW2 Settings Switch Function Default SW2 1 Serial Line 1 and 2 Routing OFF FPGA COM 1 to Faceplate FPGA COM 2 to RTM ON FPGA COM 1 to RTM FPGA COM 2 to Faceplate OFF OFF COM 1and 2 TTL level routing OFF FPGA COM 1 to Face Plate and COM 2 to RTM SW2 2 SW2 2 IPMC Debug Console Routing OFF IPMC Debug Console at 3 pin Header ON IPMC Debug Console at Faceplate instead of F...

Page 53: ...h button disabled OFF OFF Face Plate Reset push button enabled SW3 4 OFF Watchdog trigger enabled ON Watchdog trigger disabled results in cyclic IPMC Reset available only in AUTO Power mode SW100 1 ON Not available to customer powering through IPMC OFF IPMC Watchdog timer trigger is disabled only for test purposes and works only in AUTOP power mode SW100 1 ON Table 2 7 Switch SW4 Settings Switch F...

Page 54: ...and or remove DIMM memory modules in order to match the main memory size to your needs The corresponding installation removal procedures are described in this section The location of the DIMM Memory Modules are shown in Figure ATCA 7475 Blade Layout on page 50 When installing DIMM memory modules the DIMM sockets farthest away on each memory channel from the CPU device need to be populated first On...

Page 55: ... 3 to install further modules ATCA 7475 has 1 DIMM socket per Xeon memory channel Therefore usage of 2 rank DIMMs are essential for best performance Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life Before touching the module or electronic components make sure that you are working in an ESD safe environment Damage of ...

Page 56: ...7 SSD Module The SATA module consists of a Solid State Disc of up to 256 GB and a SATA controller and connects physically to PCH Sata Port 4 The MO297 SSD module is an accessory kit and is not part of the default ATCA 7475 The following procedure describes the steps to install remove the MO297 SSD module Installation Procedure To install an MO297 SSD module proceed as follows Damage of Circuits El...

Page 57: ...g the Blade on page 59 The additional resource either memory or SATA SSD will be detected automatically during the boot up sequence Removal Procedure To remove an MO297 SSD module proceed as follows 1 Remove the blade from the system as described in Installing and Removing the Blade on page 59 2 Remove the two screws holding the MO297 SSD module 3 Remove the MO297 SSD module from the blade 4 Reins...

Page 58: ...doffs fit in the blade s mounting holes 3 Fasten the Accelerator module to the blade using the three M2 5x 8mm screws 4 Reinstall the blade into the system Removal Procedure Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life Before touching the module or electronic components make sure that you are working in an ESD sa...

Page 59: ...ned to be used in AdvancedTCA shelves The blade can be installed in any AdvancedTCA node slot Do not install it in an AdvancedTCA hub slot 2 6 1 Installing the Blade To install the blade into an AdvancedTCA shelf proceed as follows Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life Before touching the blade or electroni...

Page 60: ... and bottom ejector handles are in the outward position by squeezing the lever and the latch together 2 Insert blade into the shelf by placing the top and bottom edges of the blade in the card guides of the shelf Ensure that the guiding module of shelf and blade are aligned properly 3 Apply equal and steady pressure to the blade to carefully slide the blade into the shelf until you feel resistance...

Page 61: ...ompletely installed the blue LED starts to blink This indicates that the blade announces its presence to the shelf management controller 6 Wait until the blue LED is switched off then tighten the face plate screws which secure the blade to the shelf The switched off blue LED indicates that the blade s payload has been powered up and that the blade is active 7 Connect cables to the face plate if ap...

Page 62: ...late Do not rotate the handle fully outward The blue LED blinks indicating that the blade power down process is going on 2 Wait until the blue LED is illuminated permanently then unlatch the upper handle and rotate both handles fully outward Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life Before touching the blade or...

Page 63: ...e plate cables if applicable 4 Unfasten the screws of the face plate until the blade is detached from the shelf 5 Remove the blade from the shelf Data Loss Removing the blade with the blue LED still blinking causes data loss Wait until the blue LED is permanently illuminated before removing the blade ...

Page 64: ...Hardware Preparation and Installation ATCA 7475 Installation and Use 6806800S38D 64 ...

Page 65: ...A 7475 Installation and Use 6806800S38D 65 Controls Indicators and Connectors 3 1 Face Plate The following figure illustrates the connectors keys and LEDs available at the face plate Figure 3 1 Face Plate ATCA 7475 ...

Page 66: ...PMC Note that this LED indicates the payload power status both in the early power state and the normal blade operation OFF Payload power is disabled Note This LED is multicolored red green yellow and is programmable by IPMC ATN Amber This LED is controlled by higher layer software such as middle ware or applications ETH Status LEDs The Ethernet connector provides two status LEDs Link upper Green L...

Page 67: ...e following connectors at its face plate 2x Ethernet 1x Serial 2x USB H S FRU State Machine During blade installation Permanently blue On board IPMC powers up Blinking blue Blade communicates with shelf manager OFF Blade is active During blade removal Blinking blue Blade notifies shelf manager of its desire to deactivate Permanently blue Blade is ready to be extracted Table 3 1 Face Plate LEDs con...

Page 68: ...connector is used for serial line connection Cisco like Pinout according following table is used Additinally Hardware Handshake support signals are available 3 1 3 2 Ethernet Connector There are two Ethernet connectors ETH1 connector P70 ETH2 connector P71 Table 3 2 RJ45 female Serial Line Connector pinout Pin Signal 1 COM1_CTS 2 COM1_DTR 3 COM1_RS232_TXD 4 GND 5 GND 6 COM1_RS232_RXD 7 COM1_DSR 8 ...

Page 69: ...interface to the serial interface COM1 The on board switch 2 1 allows to swap COM1 with COM2 making COM2 accessible through the face plate connector instead Note that the BIOS serial redirection feature uses COM1 as access interface Therefore swapping the serial interfaces via SW2 1 also changes the serial connector that you need to access to make use of the serial redirection feature The pinout o...

Page 70: ...rd Connectors The blade provides the following on board connectors MO297 SSD module connector ACC module connector 3 2 1 MO297 SSD Module Connector The MO297 SSD module connects to the blade through a connector that carries the following types of signals 1 SATA port PCH port 4 Power supply 5V and 3 3V Figure 3 4 USB Connector Pinout Attaching a device to the front panel USB ports that exceeds the ...

Page 71: ...s Indicators and Connectors ATCA 7475 Installation and Use 6806800S38D 71 The location of the MO297 SSD module connector is illustrated in the following figure Figure 3 5 Location of MO297 SSD Module Connector ...

Page 72: ...ion and Use 6806800S38D 72 The pinout of this connector is illustrated in the following figure Figure 3 6 MO297 SSD Module Connector Pinout SATA_TX S2 SATA_TX S3 SATA_RX S6 SATA_RX S5 GND S1 S4 S7 P4 P5 P6 P10 P12 3 3V P1 P2 P3 5V P7 P8 P9 12V P13 P14 P15 ...

Page 73: ... to 3 as specified by the AdvancedTCA standard and are called P10 P20 and P23 P30 P31 and P32 The pinouts of all these connectors are given in this section The connector residing in zone 1 is called P10 and carries the following signals Power feed for the blade VM48_x_CON and RTN_x_CON Power enable ENABLE_x IPMB bus signals IPMB0_x_yyy Figure 3 7 Location of AdvancedTCA Connectors ...

Page 74: ...ess signals HAx Ground signals SHELF_GND and GND Reserved signals Zone 2 contains the two connectors P20 and P23 They carry the following types of signals Telecom clock signals CLKx_ Base interface signals BASE_ SAS update channel 100Base BX update channel Figure 3 8 P10 Backplane Connector Pinout ...

Page 75: ...sed on the blade If the AdvancedTCA specification defines these signals as input signals they are terminated on the blade and marked as TERM_ in the following pinouts In all other cases the pins are unconnected and consequently marked as n c The pinouts of P20 and P23 are as follows Figure 3 9 P20 Backplane Connector Pinout Rows A to D Figure 3 10 P20 Backplane Connector Pinout Rows E to H ...

Page 76: ...e 3 contains the two connectors P30 P31 and P32 They are used to connect an RTM to the blade and carry the following signals Serial RS232_x_yyyy Serial ATA SATAx_yyy USB USBxy Figure 3 11 P23 Backplane Connector Pinout Rows A to D Figure 3 12 P23 Backplane Connector Pinout Rows E to H ...

Page 77: ... 77 PCI Express PCIEx_yyy IPMI IPMB1_xxx ISMB_xxx Power VP12_RTM V3P3_RTM VP5_RTM SAS Update channels General control signals BD_PRESENTx RTM_PRSNT_N RTM_RST_KEY RTM_RST Figure 3 13 P30 Backplane Connector Pinout Rows A to D Figure 3 14 P30 Backplane Connector Pinout Rows E to H ...

Page 78: ... PCIE_CPU1_P3_TX_P 14 CLK100_RTM CPU1PORT3CD DP n c PCIE_CPU1_P3_TX_N 0 PCIE_CPU1_P3_TX_N 2 PCIE_CPU1_P3_TX_N 4 PCIE_CPU1_P3_TX_N 6 PCIE_CPU1_P3_TX_N 8 PCIE_CPU1_P3_TX_N 10 PCIE_CPU1_P3_TX_N 12 PCIE_CPU1_P3_TX_N 14 CLK100 RTM CPU1PORT3CD DN n c PCIE_CPU1_P3_RX_N 1 PCIE_CPU1_P3_RX_N 3 PCIE_CPU1_P3_RX_N 5 PCIE_CPU1_P3_RX_N 7 PCIE_CPU1_P3_RX_N 9 PCIE_CPU1_P3_RX_N 11 PCIE_CPU1_P3_RX_N 13 PCIE_CPU1_P3_...

Page 79: ...Controls Indicators and Connectors ATCA 7475 Installation and Use 6806800S38D 79 Figure 3 17 P32 Backplane Connector Pinout Rows A to D Figure 3 18 P32 Backplane Connector Pinout Rows E to H ...

Page 80: ...Controls Indicators and Connectors ATCA 7475 Installation and Use 6806800S38D 80 ...

Page 81: ...r 96 on page 210 The BIOS used on the blade is based on the Phoenix UEFI BIOS with several Artesyn Embedded Technologies extensions integrated Its main features are Initialize CPU chipset and memory Initialize PCI devices Setup utility for setting configuration data IPMC support Serial console redirection for remote blade access Boot operation system The BIOS complies with the following specificat...

Page 82: ...d and treated as a normal PC keyboard input The serial console redirection feature can be configured via a setup utility 4 2 1 Requirements for Serial Console Redirection For serial console redirection the following is required Terminal or terminal emulation which supports a VT100 mode NULL modem cable Terminal emulation programs such as TeraTermPro or Putty can be used 4 2 2 Default Access Parame...

Page 83: ...a bits No parity 1 stop bit 4 2 3 Connecting to the Blade Procedure In order to connect to the blade using the serial console redirect feature proceed as follows 1 Configure terminal to communicate using the same parameters as in BIOS setup 2 Connect terminal to NULL modem cable 3 Connect NULL modem cable to COM port of the blade 4 Start up the blade 4 3 Changing Configuration Settings When the sy...

Page 84: ...the bottom of the menu Additionally an item specific help is displayed on the right side of the window Figure 4 1 Main Menu Make sure that BIOS is properly configured prior to installing the operating system and its drivers If you save changes in setup the next time the blade boots up BIOS configures the system according to the setup selections stored If those values cause the system boot to fail ...

Page 85: ...oppy CD ROM and hard disk Solid State Disk connected to the SATA interface available only when SSD SATA is assembled Storage devices connected to the SAS controller by RTM Network Front Panel Ethernet Base Ethernet and Ethernet on RTM 4 4 2 Selecting the Boot Device There are two possibilities to determine the device from which BIOS attempts to boot By setup to select a permanent order of boot dev...

Page 86: ...lows 1 From the menu select Boot 2 Select the order of the devices from which BIOS attempts to boot the operating system If BIOS is not successful at booting from one device it tries to boot from the next device on the list When BIOS does not find any bootable device the board will be restarted by a cold reset ...

Page 87: ...87 4 4 3 By Boot Menu 1 Press F4 to enter the Boot Menu 2 Override existing boot sequence by selecting another boot device from the boot list Figure 4 2 Boot Menu If the selected device does not load the operating system BIOS returns to the boot menu ...

Page 88: ... This area is read only BIOS default settings are loaded when selecting the Restore Defaults Item on BIOS Save Exit Menu A detailed description of the IPMI Boot Parameter and the corresponding IPMI commands is available in the System Boot Options Parameter 100 on page 212 The main advantage of using IPMI boot parameter is that the parameters stored as IPMI boot parameters are not changed after a B...

Page 89: ...he Flash 4 BIOS writes the parameter to the IPMI Boot Parameter USER area Load Defaults 1 User enters BIOS setup and selects Load Defaults 2 BIOS reads Default Parameter from Flash into the Setup 3 BIOS reads IPMI Boot Parameter DEFAULT area into the Setup 4 User select Save or Save and Exit option 5 BIOS writes the parameter to the BIOS Parameter in the Flash 6 BIOS writes the parameter to the IP...

Page 90: ...guration Item Values Description Front Panel Net Boot Enabled Default Disabled Controls execution of the Option ROM for the Front Panel Ethernet controller Select Enabled when Front Panel Boot is required Base Network Boot Enabled Default Disabled Controls execution of the Option ROM for both Base Network Ethernet controller Select Enabled when Base Network Boot is required ARTM Network Boot Enabl...

Page 91: ...ne No flow control RTS CTS Hardware flow control XON XOFF Software flow control Console Redirection after POST Enabled Default Disabled Enable Console Redirection after BIOS exits This is used for OS like DOS or legacy boot loader like grub Table 4 2 Main Boot Configuration Item Values Description Table 4 3 Advanced RTM Configuration Item Values Description Auto Detect RTM Enable Default Disable I...

Page 92: ...Disable Execution Disabled functionality Also known as Data Execution Prevention DEP Direct Cache Access Enable Default Disable Enable Disable Direct Cache Access Intel R Virtualization Technology Enable Default Disable When enabled a virtual machine VM can utilize the additional hardware capabilities Table 4 5 Advanced CPU Configuration Processor Power Management Item Values Description Intel R S...

Page 93: ...logy for CPU0 CPU1 DMA Enable Default Disable Enable Disable Intel Quickdata Technology DMA support for CPU0 CPU1 DCA Enable Default Disable Enable Disable Intel Quickdata Technology Direct Cache Access DCA for CPU0 CPU1 No Snoop Enable Default Disable Enable Disable Intel Quickdata Technology DMA No Snoop for CPU0 CPU1 Table 4 8 Advanced Memory Configuration Item Values Description Channel Mirror...

Page 94: ...ncorrectable Error Log Enable Disable Default Controls whether ECC uncorrectable error are logged Halt On Uncorrectable Error Enable Disable Default Controls whether to halt or not when uncorrectable errors are encountered Correctable Error Threshold Enable Disable Default Number of correctable ECC errors which must occur before they are logged Enable Correctable Error Flood Enable Disable Default...

Page 95: ... 2 Enable Default Disable Enable Disable Front Panel USB 2 port RTM USB Enable Default Disable Enable Disable USB port routed to the RTM Table 4 10 Advanced SATA Configuration Item Values Description SATA Device Enable Default Disable Enable Disable SATA device Operation Mode AHCI Default IDE Select the SATA controllers operation mode AHCI Advanced Host Controller Interface mode IDE ATA compatible...

Page 96: ...Press Enter to clear the SMBIOS event log Table 4 11 Advanced Super IO Configuration Item Values Description Table 4 13 IPMI Item Values Description IPMI KCS Interrupt Enable Disable Default Enable Disable usage of Host Interface KCS interrupt KCS interrupt is hardwired to IRQ 6 Clear Local System EventLog Enable Disable Default Clear all events in the local system event log The value will be rese...

Page 97: ...Item Values Description Table 4 14 Security Item Values Description Set Supervisor Password Press Enter to set or clear the Supervisor password Supervisor Hint String Press Enter to type the Supervisor Hint string Min password length 1 20 1 Default Set the minimum number of characters for the password HDD Password Select User Only Default User Master Supports user only or both user and master pass...

Page 98: ...r packet switching applications it is recommended to set following CPU configuration parameter seeAppendix 4 Advanced CPU Configuration Table 4 15 Exit Menu Item Values Description Exit Saving Changes Equal to F4 save all changes of all menus then exit the BIOS setup and reset the system Exit Discarding Changes Do not save changes exit the BIOS setup do not reset the system Load Setup Defaults Equ...

Page 99: ...ndent mode are Correction of any x4 DRAM device failure Detection of 99 986 of all single bit failures that occur in addition to an x4 DRAM failure Detection of any 2 bit uncorrectable errors 4 7 8 2 Mirrored Channel Mode The Integrated Memory Controller supports mirroring across channels DIMM organization in each slot of one channel must be identical to the DIMM in the corresponding slot of the o...

Page 100: ...ns of 2 x4 DRAM failures 4 8 Restoring BIOS Default Settings Thebladeprovides anon boardconfigurationswitch that allows to load BIOS settings from the DEFAULT area of the IPMI Boot Parameters In order to restore the BIOS default settings using this switch proceed as follows Procedure To restore the BIOS default settings proceed as follows 1 Remove the blade from the system See Installing and Remov...

Page 101: ...cceleration module and the RTM Logs boot error in case of no boot device found Reads the IPMI GUID and fills in the DMI structure 1 UUID Show SEL and Sensor Values in BIOS setup BIOS creates the DMI structure type 38 to provide IPMI host interface information to the OS BIOS reads and creates the IPMI boot parameter which are stored in the IPMC The list of the supported IPMI boot parameter is descr...

Page 102: ...OS event log The Runtime Error Logging can be enabled or disabled If enabled the PCI Error Logging can be enabled or disabled separately For correctable memory error logging there are two additional parameters to prevent the flooding of the event logs The parameters are Error Threshold Correctable memory errors are logged when the threshold is reached The first correctable memory error is always l...

Page 103: ...ory log disabled Sensor Memory Offset 05h Uncorrectable Uncorrectable ECC Memory Error Multi bit ECC memory error Sensor Memory Offset 01h PCI PERR PCI Parity Error Sensor Critical Interrupt Offset 04h PCI PERR PCI SERR PCI System Error Sensor Critical Interrupt Offset 05h PCI SERR Table 4 17 Logged Error Events continued Error SMIBIOS IPMI ...

Page 104: ...BIST Error 22h PCI Out Of Resource 50h IPMI Boot Parameter Default Area Read Error 51h IPMI Boot Parameter Default Area Locked 52h IPMI Boot Parameter Default Area Checksum Error 53h IPMI Boot Parameter User Area Read Error 54h IPMI Boot Parameter User Area Locked 55h IPMI Boot Parameter User Area Checksum Error 56h IPMI Boot Parameter User Area Write Error 60h North Bridge Error 62h No Space for ...

Page 105: ...n 0 3 DIMM number 1 8 Fh DIMM number unknown 4 DIMM number per Channel 0 1 5 6 DIMM channel 0 2 7 CPU Socket 0 1 See naming convention for DIMM Figure ATCA 7475 Blade Layout on page 50 Critical Interrupt 13h Offset 04h PCI PERR Offset 05h PCI SERR Event Data2 Bus number Event Data 3 Bit Description 0 3 PCI Function number 4 7 PCI Device number Boot Error 1Eh Offset 00h No bootable media no boot de...

Page 106: ...Single bit ECC memory error Multi bit ECC memory error System Firmware Progress 0Fh Offset 00h System Firmware Error Supported Event Data3 70h Front Panel Network not detected 78h Base Network not detected 79h Base Network reduced PCI performance 7Ah Base Network Device Error 80h Fabric Network not detected 81h Fabric Network reduced PCI performance 82h Fabric Network Device Error 88h Update Chann...

Page 107: ...CC Memory Error This event is generated from the runtime error logging module See Runtime Error Logging on page 102 Table 4 19 Single bit ECC Memory Error event format Offset Name Format Description 00h Event Type BYTE Event Type 01h 01h Length BYTE always 0Ch 02h 07h Date Time Fields BYTE These fields contain the BCD representation of the date and time 08h 0Bh Memory Information UINT32 OEM extens...

Page 108: ... generated 24 31 CPU Socket 0 1 Table 4 20 Memory Information Definition continued Bit Description Table 4 21 Multi bit ECC Memory Error Event Format Offset Name Format Description 00h Event Type BYTE Event Type 02h 01h Length BYTE always 0Ch 02h 07h Date Time Fields BYTE These fields contain the BCD representation of the date and time 08h 0Bh Memory Information UINT32 OEM extension Table 4 22 Mem...

Page 109: ...WORD UINT32 See Table 4 24 on page 109 0Ch 0Fh Result Second DWORD UINT32 See Table 4 25 on page 109 Table 4 24 Result First DWORD supported POST Errors Bit Description 3 CMOS RAM Battery Failure Battery is bad removed or replaced 9 Keyboard Not Functional No console input device found or device error 12 Memory Decreased in Size DIMM errors during memory initialization found Failed DIMM disabled 1...

Page 110: ...el Network Error 7 PCI Memory Conflict 17 Static Resource Conflict e g No Space for OPROM 19 System Board Device Resource Conflict 20 Primary Output Device Not Found 24 NVRAM Data Invalid Flash write error Table 4 25 Result Second DWORD supported POST Errors continued Bit Description Table 4 26 PCI Parity Error Event Format Offset Name Format Description 00h Event Type BYTE Event Type 09h 01h Leng...

Page 111: ...ved 8 15 PCI Function 16 23 PCI Device 24 31 PCI Bus number Table 4 28 Multi bit ECC Memory Error Event Format Offset Name Format Description 00h Event Type BYTE Event Type 0Ah 01h Length BYTE always 0Ch 02h 07h Date Time Fields BYTE These fields contain the BCD representation of the date and time 08h 0Bh PCI Information UINT32 OEM extension Table 4 29 Memory Information Definition Bit Description...

Page 112: ...re Event Format Offset Name Format Description 00h Event Type BYTE Event Type 0Bh 01h Length BYTE always 0Ch 02h 07h Date Time Fields BYTE These fields contain the BCD representation of the date and time Table 4 31 Correctable Memory Log Disabled Event Format Offset Name Format Description 00h Event Type BYTE Event Type 01h 01h Length BYTE always 0Ch 02h 07h Date Time Fields BYTE These fields cont...

Page 113: ...r all LEDs U1 U2 and U3 are set to red Shortly before closing BIOS and starting an operation system U3 is switched off 4 13 Upgrading the BIOS A BIOS upgrade kit for the blade is available This allows the BIOS to be upgraded The Table 4 33 Log Area Reset Cleared Event Format Offset Name Format Description 00h Event Type BYTE Event Type 16h 01h Length BYTE always 08h 02h 07h Date Time Fields BYTE T...

Page 114: ...is only valid when the board is in the BIOS phase The reading canbeusedtolocatethecauseofaboardhangduringBIOSphase Whentheboardhasbooted a OS the reading of the POST code sensor returns no valid status code For debugging purpose the POST Codes can be printed to the serial console by setting DIP Switch 4 3 and 4 4 to ON After performing a BIOS upgrade or after restoring a corrupted BIOS image all B...

Page 115: ...t 0x34 USB Legacy Init 0x35 Data Hub Init DXE 0x36 Device Path 0x37 Info Screen Init 0x38 Disk IO DXE 0x39 IPL DXE 0x3C Error Log PEI DXE SMM 0x3D Read FAT File System PEI DXE 0x3E Firmware Device DXE SMM 0x3F Firmware Find PEI 0x41 Flash Communication DXE SMM 0x45 Hard Disk Password 0x46 Hii Database Init 0x47 Form Browser Core DXE 0x48 Form Browser Simple Text View Layout 0x49 Form Browser Simpl...

Page 116: ...onome DXE 0x59 Metronome RT 0x5B OEM Activation 0x5C Partition Module 0x5E PCI Bus Init 0x60 Progress Module 0x64 RTC DXE SMM 0x65 Runtime Init 0x67 S3 Resume PEI Save DXE 0x68 SCSI Bus Init 0x69 SCSI Disk Init 0x6A SCSI OPROM Pass Thru DXE 0x6B CRC32 Section Extract DXE 0x6D Flash Hob PEI Trap SMM 0x70 Security Stub DXE 0x71 Serial Terminal Init 0x72 Setup Init 0x73 SMBIOS Init 0x74 SMBIOS Event ...

Page 117: ...80 English DXE 0x81 USB Bus Init DXE 0x82 EHCI Init PEI DXE 0x83 USB Device Init 0x84 USB Protocol 0x85 User Manager 0x87 Variable Service PEI DXE SMM 0x88 VGA DXE 0x89 WHEA DXE SMM 0x91 PCH Flash Controller 0xA0 Platform Init Stage 0 0xA1 Platform Init Stage 1 0xA3 Platform Init DXE 0xA4 S3 Save 0xA5 Platform Flash DXE SMM 0xA6 Platform SMM 0xA9 Platform Setup Advanced Init 0xAA Platform Setup Ta...

Page 118: ...PI Initialization Link Layer Settings 0xAE QPI Initialization Coherency Settings 0xAF QPI Initialization QPI Done 0xB0 Memory Initialization DIMM Detect 0xB1 Memory Initialization Clock 0xB2 Memory Initialization Read SPD data 0xB3 Memory Initialization Early Init 0xB4 Memory Initialization Rank Detection 0xB5 Memory Initialization Early Channel Init 0xB6 Memory Initialization JEDEC Init 0xB7 Memo...

Page 119: ...r S3 Resume 0xE9 Memory Init Error Register Lock 0xEA Memory Init Error DIMM Initialization 0xEB Memory Init Error Memory Test 0xEE Memory Init Error Compatibility Error 0xEF Memory Init Error Internal Error Boot Mode 0xF0 Reset Vector 0xF1 Leaving SEC Entering PEI 0xF2 Entering PEI Dispatch 0xF3 Exiting PEI Dispatch 0xF4 Entering DXE IPL normal Boot Path 0xF5 Entering DXE IPL S3 Boot Path 0xF6 Ex...

Page 120: ...Dispatch 0xFA Exiting DXE Dispatch 0xFB No Memory found at the end of PEI 0xFC No DXE IPL found at the end of PEI 0xFD No DXE found at the end of IPL 0xFE No PPIs found by DXE 0xFF Missing arch protocols at the end of DXE Table 4 35 BIOS Status Codes POST Code Description ...

Page 121: ... Installation and Use 6806800S38D 121 Functional Description 5 1 Block Diagram The block diagram shows how the devices work together and the data paths used Figure 5 1 Block Diagram ATCA 7475 V2 10 V2 10 1866 1866 600 600 ...

Page 122: ...evice LGA2011 socket R The processors are connected with each other through 2 Intel QuickPath Interconnect point to point links capable of up to 8 GT s both Xeon CPUs provide an integrated 4 channel DDR3 Memory Controller IMC 5 3 Memory The Xeon CPU features an integrated DDR3 memory controller The memory controller provides four independent memory channels that allow flexible memory configuration...

Page 123: ...ory Error signaling for correctable memory errors ADR feature to support persistent memory structures in DDR3 asynchronous DRAM refresh 5 4 Platform Controller Hub PCH TheNextGenerationCommunicationsPlatformControllerhub codenameCrystalForest Intel DH8900CCPCHprovidesaccessbetweenprocessorsandtheI Osubsystem ThePCHprovides two different complexes PCH I O controller connected to DMI2 interface of C...

Page 124: ...e RTM Serial Over LAN support SMB Pass through Two stage Watchdog timer WDT D31 F7 SPI Interface Boot Flash up to two devices 20 33MHz LPC Interface Two serial ATA SATA controllers D31 D2 for AHCI mode and D31 F5 Native IDE mode for up to 6 physical SATA ports Six USB 2 0 interfaces through one EHCI host controller D29 F0 Power management support D31 F0 including ACPI S3 state support suspend to R...

Page 125: ...0 100 1000Base T provide two Faceplate 10 100 1000Base T interfaces The PCH Intel QuickAssist Technology supports following features in Hardware and through a Software SDK Security Encryption Decryption up to 20Gbps Bulk AES 3Des A RC4 Hash MD5 SHA 1 2 HMAC Wireless Kasumi and SNOW 3G Public Key RSA DSA DH Internal TRNG pCRC Security Encryption Decryption up to 20Gbps Compression Decompression Def...

Page 126: ...he I O functions provided by Intel Cavecreek PCH and those used on ATCA 7475 5 5 Firmware Flashes The Blade has two physically separate 8 MB flash devices hosting the BIOS firmware Primary or Default BIOS Flash SPI 0 Recovery BIOS Flash SPI 1 Figure 5 2 Intel Cavecreek PCH on ATCA 7475 Block Diagram ...

Page 127: ... 1000Base KX Option1 1 K 1 KR 9 9 K 9 KR The redundant fabric I F is fully operable in 40G 10G or 1G mode without the presence of an RTM Two 10 100 1000Base T Ethernet ports are available on the front panel Additional Ethernet ports for external access are provided via different RTMs The Ethernet controllers support I O virtualization 5 6 1 ATCA Base IF Link Status Pass Through Thelinkstatus linku...

Page 128: ...driver will detect the link change and can propagate this information MDIO Interface can be implemented as Bit Bang Interface or FPGA can handle the Interface 5 6 1 1 Marvel Switch Initialization Enable Marvel Switch Interrupt generation for Base 1 and Base 2 example P0 and P1 Copper Specific Interrupt PHY Register Page 0 Register 18 Bit 10 Link Status Changed Interrupt Enable PHY Port 0 1 Led0 co...

Page 129: ...ations The Sata interface is compliant to SATA 3Gb s speed 5 9 BIOS ATCA 7475providesaBIOSfirmwarethatisstoredinflashmemory Itcanbeupdatedremotely via Ethernet or locally via operating system Along with the BIOS and BIOS Setup program the flash memory contains POST and Plug and Play support The BIOS displays a message during POST identifying the type of BIOS and a revision code A BIOS extension is...

Page 130: ...de temperature sensor readings at all major devices and voltage sensor readings of all major voltages The IPMC monitors reset events caused by devices like Watchdog IPMI command and reset button The FRU informationofthevariousmodulesincludingfrontboard RTM andothermodulescanberead via the IPMC and if necessary upgraded thru the IPMC The IPMC features Serial over LAN SOL for the payload CPU serial ...

Page 131: ...deband connection to the Base I F Vice versa the Ethernet controller filters packets based on either MAC address RMCP port number or IP address and forwards them to the serial redirection over the sideband interface Client software like openIPMI is required to enable SOL and to communicate with the SOL based serial console 5 13 Control Logic The blade provides control logic for specific functions ...

Page 132: ...900CC PCH and routed to the onboard FPGA which distributes them to either Faceplate RTM or IPMC for SOL The serial line interfaces support baud rates up to 115200 kbps through a programmable baud rate generator Serial Line Interface 1 COM 1 and 2 COM 2 destination The serial line interface 1 2 can be routed either to the zone 3 connector or the Faceplate Destination selection is through IPMC or SW...

Page 133: ...at the faceplate are routed to a dual stacked connector The ports are USB 2 0 compliant 5 17 LPC Interface The PCH provides a 4 bit wide low pin count LPC interface running at 33MHz is connected to following onboard I O devices Glue Logic FPGA register map IPMC Controller TPM Extension Module Header 5 18 Trusted Platform Module The Trusted Platform Module TPM is a specific protected and encapsulat...

Page 134: ...es 256 bytes of backed up CMOS RAM of which 14 bytes contain the RTC time and date info and RTC configuration During power down the RTC consumes 0 9uA hr Default power down backup solution is an external 3V lithium battery with a capacity of 200mAh which provides 3 years of backup Optional power down backup method uses a Super CAP with a 1 Farad capacity This provides 300 hours of RTC SRAM backup ...

Page 135: ...or voltage level translation to buffer the SMBus portion going to the SPD PROMs on the DIMM Table 5 4 Variants of the Intel DH8900CC PCH Device Devices Intel DH8900CC SKU1 Entry Level Intel DH89xxCC SKU2 Entry Level Intel DH89xxCC SKU3 Mid Performance IntelDH8920CCSKU4 Max performance Usage on ATCA 7475 Carrier board I O controller hub 4xMAC OptionalQuickAssist engine with SKU2 Acceleration Module...

Page 136: ...hitecture Table 5 6 SMBus Address Map Device Name Device Type Location SMBus Controller Address SPD EEPROM 24C02 CPU0 CH 0 A DIMM 1 CPU 0 SMB AB 1010 000x b A0 SPD EEPROM 24C02 CPU0 CH 1 B DIMM 1 CPU 0 SMB AB 1010 100x b A8 SPD EEPROM 24C02 CPU0 CH 2 C DIMM 1 CPU 0 SMB CD 1010 000x b A0 SPD EEPROM 24C02 CPU0 CH 3 D DIMM 1 CPU 0 SMB CD 1010 100x b A8 ...

Page 137: ...27 Base Board CPU 1 SMB CD 0x5C PCH SMB Slave Intel DH8920CC PCH 0x88 RCV_SLVA default Temp Sens 0 LM75 Base Board Intel DH8900CC 0x90 Temp Sens 1 LM75 Base Board Intel DH8900CC 0x92 Clock generator CK420B Base Board Intel DH8900CC 0xD2 DB1900Z clock DB1900Z Base Board Intel DH8900CC 0xD8 Intel Cavecreek PCHSlaveSMBus IF Intel DH8900CC Base Board Intel DH8900CC 0xE0 IOH Bootstrap SMBUSID option is...

Page 138: ...Functional Description ATCA 7475 Installation and Use 6806800S38D 138 ...

Page 139: ...ek PCH supports 16 interrupts 8 external signal inputs The IO APIC device inside the Intel Cavecreek PCH supports 24 interrupt sources In APIC mode the Intel Cavecreek PCH supports only Front side bus interrupt delivery not the serial APIC mode The following figure summarizes the interrupt sources and mappings for ATCA 7475 APIC mode is configured through BIOS after boot up phase which is done in ...

Page 140: ...RQ4 via SERIRQ PIRQ 5 Parallel Generic IRQ5 via SERIRQ PIRQ 6 Floppy IRQ6 via SERIRQ PIRQ 7 Parallel Generic IRQ7 via SERIRQ PIRQ Slave 0 Internal RTC Internal RTC HPET 1 1 Generic IRQ9 via SERIRQ SCI TCO or PIRQ 2 Generic IRQ10 via SERIRQ SCI TCO or PIRQ 3 Generic IRQ11viaSERIRQ SCI TCO orPIRQ orHPET 2 4 PS 2 Mouse IRQ11 via SERIRQ SCI TCO or PIRQ or HPET 3 5 Internal State Machine output based o...

Page 141: ...es 7 Yes No Yes 8 No No No RTC Timer 1 legacy mode 9 Yes No Yes Option for TCI TCO 10 Yes No Yes Option for TCI TCO 11 Yes No Yes HPET 2 Option for TCI TCO 12 Yes No Yes HPET 3 13 No No No FERR logic 14 Yes No Yes SATA Primary legacy mode 15 Yes No Yes SATA Secondary legacy mode 16 PIRQA PIRQ A Yes Internal devices are routable 17 PIRQB PIRQ B Yes Internal devices are routable 18 PIRQC PIRQ C Yes ...

Page 142: ...are described In the following table 21 N A PIRQ F 1 Yes Option for SCI TCO and HPET 0 1 2 3 For other internal devices are routable 22 N A PIRQ G 1 Yes Option for SCI TCO and HPET 0 1 2 3 For other internal devices are routable 23 N A PIRQ H 1 Yes Option for SCI TCO and HPET 0 1 2 3 For other internal devices are routable Table 6 2 APIC Mode Interrupt Mapping continued IRQ Via SERIRQ Direct from ...

Page 143: ...aneous Registers Post Code Register Version Register SPI boot flash control Boot device selection control Support of several board control status signals Port80 7Seg Debug Led control COM Port routing Port 1 Faceplate or RTM Port 2 IPMC Serial over LAN Some of the internal functions are connected to the LPC bus via the corresponding bus interface to the internal local bus and some other internal f...

Page 144: ...A 6 3 Registers For register description the convention shown in Table 1 Register Default and Table 2 Register Access Type are used Figure 6 2 Glue Logic FPGA Block Diagram Table 6 4 Register Default Default Description Not applicable or undefined 0 or 1 Default value after PWR_GOOD is valid or after PCH_PLTRST_ deassertion Undef Undefined value ...

Page 145: ...escription r Read only w Write only r w Read and write w1c Write 1 to clear ignore bit while reading r w1c Read and write 1 to clear write 0 has no effect r w1s Read and write 1 to set write 0 has no effect r w1t Read and write 1 to toggle write 0 has no effect LPC The prefix LPC signals that the access is restricted to the LPC interface For example LPC r w means that the register bit is readable ...

Page 146: ... accesses 6 3 1 2 SPI Register Decoding All SPI accesses from the IPMC towards the FPGA with the SPI select signal IPMC_SPI_SS_FPGA_ asserted are accepted 6 3 2 POST Code Register The FPGA provides an 8 bit wide register to store POST codes to the LPC I O address 0x80 The two nibbles of the register are converted to 7 segment codes and are displayed as two hex values by two 7 segment LED Displays ...

Page 147: ...The IPMC can read the POST code using the SPI interface with the signal IPMC_SPI_SS_FPGA_ asserted and the SPI address 0x7F Table 6 8 POST Code Register LPC I O Address 0x80 IPMC SPI Address 0x7f Bit Description Default Access 7 0 POST codes from host 0 LPC r w IPMC r ...

Page 148: ...MC SPI Register Map The FPGA registers may be accessed via IPMC SPI transactions with the signal IPMC_SPI_SS_FPGA_ asserted See Table FPGA Register Map Overview on page 148 An SPI write access to an address not listed in this table or not marked with an X in the IPMC SPI column is ignored A corresponding read access delivers always zero The address offsets not mentioned below are not used Table 6 ...

Page 149: ...DR Configuration Register 0x19 x x Software Reset Register 0x1A Reserved 0x1B x x FWH_PLTRST_ Enable Register 0x1C 0x1F Reserved 0x20 x External Interrupt Status Register 0x21 x x Processor Hot Status Register 0x22 x Telecom Status Control Register 0x23 0x2E x Interrupt Mask and Map Registers 0x2F x BASE IF Link Interrupt Status Register 0x30 0x37 x x CPU 0 PCI Express Hot Plug I2C IO Expander Reg...

Page 150: ...tatus Signals Register 0x57 x x Miscellaneous Status Control Register 0x58 0x5B Reserved Not used 0x5C 0x6F x Telecom Clock control and supervision Registers 0x70 x MII Management Interface PHY Address Register 0x71 x MII Management Interface Control and Address Register 0x72 x MII Management Interface Lower Byte Register 0x73 x MII Management Interface Upper Byte Register 0x74 0x79 Reserved Not u...

Page 151: ...h new release 6 4 5 Serial Redirection Control Register BIOS sets the corresponding bit which is used for serial redirection The IPMC uses this information to route the corresponding port to serial IPMC interface in case of SOL Table 6 10 Module Identification Register Address Offset 0x00 Bit Description Default Access 7 0 ATCA 7475 Module Identification 0x70 r Table 6 11 Version Register Address ...

Page 152: ...al redirection 1 COM1 used for serial redirection 0 LPC r w IPMC r 1 COM2 used for serial redirection 0 COM2 not used for serial redirection 1 COM2 used for serial redirection 0 LPC r w IPMC r 7 2 Reserved 0 r When both control bits are enabled bit 1 is ignored Table 6 13 Serial over LAN Control Register Address Offset 0x04 Bit Description Default Access 0 SOL over COM1 enable 0 disabled 1 enabled...

Page 153: ...ment there is no ARTM with an SPI interface defined Table 6 14 Serial Line Routing Register Address Offset 0x05 Bit Description Default Access 1 0 Inverted level of signals SEL_SERIAL 1 0 which are controlled by switches SW2 2 and SW2 1 Switch setting may be overwritten by IPMC Software 00 COM1 to Face Plate and COM2 to RTM 01 COM1 to RTM and COM2 to Face Plate 10 Reserved 11 Reserved Ext SW2 21 S...

Page 154: ...ce A write access to the RTM SPI Address Command Register with the Command Bit 1 Read starts an SPI read transaction This contains the data read from the SPI device Table 6 15 RTM SPI Address Command Register Address Offset 0x08 Bit Description Default Access 0 Command Bit 0 Write 1 Read 0 LPC r w 7 1 RTM SPI Address bits 6 0 0 LPC r w Table 6 16 RTM SPI Write Register Address Offset 0x09 Bit Desc...

Page 155: ...cent reset 1 in the register bit indicates that the associated reset has occurred If more than one reset occurs from different sources without clearing the corresponding register bits one cannot determine the most recent reset source since more than one bit will be set The same situation occurs if two reset sources go active at the same time Table 6 18 DIMM ADR Status Register Address Offset 0x0A ...

Page 156: ...10 Bit Description Default Access 0 PWR_GOOD Payload Power on reset 1 Reset occurred PWR_GOOD 1 LPC r w1c IPMC r 1 XDPx reset request Any one of XDPx signal caused reset 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r 2 PB_RST_ face plate push button reset 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r 3 PCH_WDT_TOUT_ reset 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r 4 RTM_PB_RST_ Reset key at RTM 1 R...

Page 157: ...3 3 is OFF 0 SW3 3 is ON r w 3 Reserved 0 r 4 RTM_PB_RST_ Reset key at RTM 1 enabled 0 disabled Ext FACE_PB_EN 1 SW3 3 is OFF 0 SW3 3 is ON r w 7 5 Reserved 0 r Table 6 20 Reset Mask Register continued Address Offset 0x11 Bit Description Default Access OS should never write to this register Table 6 21 BIOS IPMC Watchdog Timeout Register Address Offset 0x12 Bit Description Default Access 0 BIOS IPM...

Page 158: ... the BIOS Reset Source Register 1 in the register bit indicates that the associated reset has occurred If more than one reset occurs from different sources without clearing the corresponding register bits one cannot determine the most recent reset source since more than one bit will be set This occurs if two reset sources go active at the same time After a timeout of 8s the resets are armed again ...

Page 159: ...curred PWR_GOOD 1 LPC r w1c IPMC r 1 XDPx reset request Any one of XDPx signal caused reset 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r 2 PB_RST_ face plate push button reset 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r 3 PCH_WDT_TOUT_ reset 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r 4 RTM_PB_RST_ Reset key at RTM 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r 5 INTEL_INIT3V3_ PCH output 1 Event ...

Page 160: ...ster Address Offset 0x15 Bit Description Default Access 0 OS IPMC Watchdog Timeout 1 IPMC Watchdog Timeout occurred PWR_GOOD 0 LPC r w1c IPMC r 1 OS IPMC Pre Timeout 1 IPMC Pre Timeout occurred PWR_GOOD 0 LPC r w1c IPMC r 7 2 Reserved 0 r IPMC clears the IPMC watchdog timeout bit to arm IPMC watchdog timeout event recognition Table 6 25 IPMC Watchdog Timeout Register Address Offset 0x16 Bit Descri...

Page 161: ...ve at the same time Table 6 26 IPMC Reset Source Register Address Offset 0x17 Bit Description Default Access 0 PWR_GOOD Payload Power on reset 1 Reset occurred PWR_GOOD 1 IPMC r w1c 1 XDPx reset request Any one of XDPx signal caused reset 1 Reset occurred PWR_GOOD 0 IPMC r w1c 2 PB_RST_ face plate push button reset 1 Reset occurred PWR_GOOD 0 IPMC r w1c 3 PCH_WDT_TOUT_ reset 1 Reset occurred PWR_G...

Page 162: ...of 30 us If ADR is not enabled PCH_SYS_RST_ is generated immediately without the assertion of PCH_ADR_IRQ_ signal Table 6 27 DIMM ADR Feature Configuration Register Address Offset 0x18 Bit Description Default Access 0 ADR enable for Push button reset 1 ADR enabled 0 ADR disabled PWR_GOOD 0 LPC r w IPMC r w 1 ADR enable for RTM Push button reset 1 ADR enabled 0 ADR disabled PWR_GOOD 0 LPC r w IPMC ...

Page 163: ...Once enabled the FWH_PLTRST_ is directly connected to the PCH_PLTRST 6 4 11 Interrupt Control and Status Registers The interrupt status registers indicate the status of the interrupt input signals They are read only registers When an interrupt is active the corresponding status bit is read 1 Write access to these register bits does not have any impact Table 6 28 Software Reset Control Register Add...

Page 164: ...sponding status bit is read 1 Description Default Access 0 IPMC2HOST_INT_ IPMC signals interrupt Ext LPC r 1 LM75_INT_ Interrupt input from payload Temp sensor Ext LPC r 2 ETH_BASE_INT_ IRQ request from 88E6161 Marvell Switch Ext LPC r 3 ETH_FP_INT_ IRQ request from 88E1322 Marvell PHY Ext LPC r 4 Reserved Reserved 0 r 5 THERM_ALERT_ IRQ request from IOH Thermo sensor Ext LPC r 6 APB_ALARM An 48V ...

Page 165: ...l temperature 1 CPU0 is overheated Ext LPC r 1 CPU1_PRCHT_ indicates if CPU1 is Hot 0 Normal temperature 1 CPU1 is overheated Ext LPC r 3 2 Reserved Ext LPC r w 4 Reflects the status of the signal IPMC_THROTTLE_REQ LPC r 5 Reflects the status of the signal PCH0_THROTTLE_REQ Ext LPC r 6 Reflects the status of the signal CPU0_VRHOT_ Ext LPC r 7 Reflects the status of the signal CPU1_VRHOT_ Ext LPC r...

Page 166: ...vent 2 Reflects Interrupt signal LCCB_INTREQ_ from ACS telecom clock device 0 not asserted High 1 asserted Low Ext LPC r 3 Reserved 0 r 6 4 Enable for Telecom interrupt events 0 to 2 0 interrupt is disabled 1 Interrupt is enabled 0 LPC r r 7 Reserved 0 r Table 6 32 Telecom Interrupt Control Status Register continued Address Offset 0x22 Bit Description Default Access Table 6 33 Address Map of Inter...

Page 167: ...us of the Base interface 2 0x2A CPU0_PRCHT_ CPU0 Processor hot interrupt 0x2B CPU1_PRCHT_ CPU1 Processor hot interrupt 0x2C Telecom Interrupt Telecom Interrupt Not implemented 0x2D RTM_SPI_MISO RTM interrupt sources 0x2E Table 6 33 Address Map of Interrupt Mask and Map Registers continued Interrupt Source Description Address Offset of Interrupt Mask ...

Page 168: ... 0x01 Frame number 1 IRQ0 0x02 Frame number 2 IRQ1 0x03 Frame number 3 IRQ2 SMI_ 0x04 Frame number 4 IRQ3 0x05 Frame number 5 IRQ4 0x06 Frame number 6 IRQ5 0x07 Frame number 7 IRQ6 0x08 Frame number 8 IRQ7 0x09 Frame number 9 IRQ8 0x0A Frame number 10 IRQ9 0x0B Frame number 11 IRQ1 0x0C Frame number 12 IRQ11 0x0D Frame number 13 IRQ12 0x0E Frame number 14 IRQ13 0x0F Frame number 15 IRQ14 0x10 Fram...

Page 169: ...mapped to 0x38 0x3F 6 5 An external Interrupt Signal CPU_IRQ_X_ is used Only used when IRQ Frame Number is 0x00 0x0 Interrupt is masked disabled 0x1 Map Interrupt to CPU_IRQ_A_ 0x2 Map Interrupt to CPU_IRQ_B_ 0x3 Reserved 0 LPC r w 7 Reserved 0 r Table 6 34 Interrupt Mask and Map Registers continued Address Offset 0x23 0x2E Bit Description Default Access Table 6 35 Base Link Interrupt Status Regis...

Page 170: ...ecise definition refer to PCI Express Base Specification Revision 3 0 Ext r 1 PWRLED Output This indicator is connected to the Power LED on the baseboard For a precise definition refer to PCI Express Base Specification Revision 3 0 Ext r 2 PWREN Output Output signal allowing software to enable or disable power to a PCI Express slot Ext r 3 BUTTON Input Input signal per slot which indicates that th...

Page 171: ...is used to electromechanically hold the card in place and is operated by software MRL is usedforcard edgeandEMLSTS isusedfor SIOM form factors 1 IPMC r w LPC r 7 EMIL Output Electromechanical retention latch control output that opens or closes the retention latch on the board for this slot A retention latch is used on the platform to mechanically hold the card in place Refer to PCI Express Server ...

Page 172: ...ave address 0x20 0x34 CPU0 Device2 Slave address 0x21 0x36 CPU1 Device1 Slave address 0x20 0x3C CPU1 Device1 Slave address 0x21 0x3E Bit Description Default Acces s 2 0 Internal PCA9555 register address 0 r w 7 3 Reserved 0 r Table 6 38 Content of PCA9555 Internal Register Address Offset CPU0 Device1 Slave address 0x20 0x35 CPU0 Device2 Slave address 0x21 0x37 CPU1 Device1 Slave address 0x20 0x3D ...

Page 173: ...W1 1 OFF 1 SW1 1 ON LPC r 1 Recovery Boot SPI Flash Write protection Status SeeTable Recovery Boot SPI Flash Write Enable on page 174 how to disable write protection 0 Recovery Boot SPI Flash is unprotected 1 Recovery Boot SPI Flash is protected Ext BOOT_REC_WP_2 0 SW1 2 OFF 1 SW1 2 ON LPC r 3 2 Reserved 0 LPC r 4 TSOP or PLCC Boot select Signal BOOT_TSOP 0 TSOP selected 1 PLCC selected Ext 0 SW1 ...

Page 174: ...when PCH_PLTRST_ is deasserted 2 The default is latched from SW1 2 when PCH_PLTRST_ is deasserted Table 6 40 Default Boot SPI Flash Write Enable Address Offset 0x41 Bit Description Default Access 7 0 Default Boot SPI Flash Write enable disable A write value 0xC3 enables the Boot Block All other values disables the Boot Block LPC w Table 6 41 Recovery Boot SPI Flash Write Enable Address Offset 0x42...

Page 175: ... Mode Ext 1 SW4 3 ON 0 SW4 3 OFF r Ext 1 SW4 4 ON 0 SW4 4 OFF r 7 2 Reserved 0 r Table 6 43 Update Channel Equalization Control Register Address Offset 0x48 Bit Description Default Access 0 Control output Signal UC1_EQ_RX 0 UC1_EQ_RX is driven low 1 UC1_EQ_RX is tri state 0 LPC r w IPMC r 1 Control output Signal UC1_EQ_TX 0 UC1_EQ_TX is driven low 1 UC1_EQ_TX is tri state 0 LPC r w IPMC r 2 Contro...

Page 176: ...X is tri state 0 LPC r w IPMC r 6 Control output Signal UC4_EQ_RX 0 UC4_EQ_RX is driven low 1 UC4_EQ_RX is tri state 0 LPC r w IPMC r 7 Control output Signal UC4_EQ_TX 0 UC4_EQ_TX is driven low 1 UC4_EQ_TX is tri state 0 LPC r w IPMC r Table 6 43 Update Channel Equalization Control Register continued Address Offset 0x48 Bit Description Default Access Table 6 44 IPMC E Keying Status Register Addres...

Page 177: ... Disable Enable USB Port 2 to RTM 0 RTMUSB_ENABLE_ driven low Enabled 1 RTMUSB_ENABLE_ driven high Disabled PWR_GOOD 1 LPC r w IPMC r w 7 2 Reserved 0 r Table 6 46 LED Status and Control Register Address Offset 0x50 Bit Description Default Access 0 Control green LED output Signal LED_GREEN_ 0 LED_GREEN_ is driven high 1 LED_GREEN_ is driven low 0 LPC r w IPMC r 1 Control red LED output Signal LED_...

Page 178: ...l Register continued Address Offset 0x50 Bit Description Default Access Table 6 47 CPLD Version and Spare Signal Status Register Address Offset 0x51 Bit Description Default Access 2 0 CPLD Version The CPLD uses the signals CPLD_REV_BIT 2 0 Ext r 7 3 Reserved 0 r Table 6 48 Spare Signal Status Register Address Offset 0x52 Bit Description Default Access 0 Reserved 0 r 1 Signal level of CPLD_SPARE Ex...

Page 179: ...it Description Default Access 0 Shows the status of DIMM Event signal from CPU0 Channel 0 A Ext r 1 Shows the status of DIMM Event signal from CPU0 Channel 1 B Ext r 2 Shows the status of DIMM Event signal from CPU0 Channel 2 C Ext r 3 Shows the status of DIMM Event signal from CPU0 Channel 3 D Ext r 4 Shows the status of DIMM Event signal from CPU1 Channel 0 E Ext r 5 Shows the status of DIMM Eve...

Page 180: ... Identification Status of signal CPU1_TYPE_IVY_ 0 IVY Bridge 1 Sandy Bridge Ext r 2 CPU0 Presence Detection Status of signal CPU0_SKTOCC_ 0 CPU present in socket 1 CPU not present Socket is empty Ext r 3 CPU1 Presence Detection Status of signal CPU1_SKTOCC_ 0 CPU present in socket 1 CPU not present Socket is empty Ext r 7 4 Reserved 0 r Table 6 51 Memory Temperature Status Register Address Offset ...

Page 181: ...e status of CPU1 memory channel 2 3 0 Temperature threshold crossed 1 Normal working temperature Ext r 4 Temperature status of the CPU0 memory voltage regulator 0 Temperature threshold crossed 1 Normal working temperature Ext r 5 Temperature status of the CPU1 memory voltage regulator 0 Temperature threshold crossed 1 Normal working temperature Ext r 7 6 Reserved 0 r Table 6 51 Memory Temperature ...

Page 182: ... from Sandybridge EP CPUs to Cavecreek Bit 0 Hardware correctable error no operating system or firmware action required Bit 1 Non fatal error operating system or firmware action required to contain and recover Bit 2 Fatal error system reset likely required to recover Ext r 1 FM_ERR_ 1 Ext r 2 FM_ERR_ 2 Ext r 3 PCH0_PCIE_WIDTH PCH PCIE interface status 0 PCIE x4 to RTM port 6 1 PCIE x1 to VGA Ext r...

Page 183: ... 53 Misc Ethernet Link and CPU Error Status Register continued Address Offset 0x57 Bit Signal Description Default Access Table 6 54 ACS8225B SPI Access Register Address Offset 0x5C Bit Description Default Access 6 0 ACS8825B SPI Address max 128 bytes CPU_PWROK 0 LPC r w 7 SPI Command 0 Write ACS8525B Register Triggers 16 SPI clocks and shifts the address and data out to MOSI 1 Read ACS8525B Regist...

Page 184: ...ad data register Contains read data after SPI address and command written CPU_PWROK 0 LPC r Table 6 55 ACS8225B SPI Status Register continued Address Offset 0x5D Bit Description Default Access SP should read or write to the XACS8225B SPI Access RegisterX only when Busy Bit in ACS8225B SPI Status Register is not set Table 6 57 ACS8225B Status Control Register Address Offset 0x5F Bit Description Def...

Page 185: ... Enable and Routing Register Address Offset 0x60 Bit Description Default Access 0 CLK3A Enable signal 0 drive LCCB_CLK3A_EN low 1 drive LCCB_CLK3A_EN high PWR_GOOD 0 LPC r w 1 CLK3B Enable signal 0 drive LCCB_CLK3B_EN low 1 drive LCCB_CLK3B_EN high PWR_GOOD 0 LPC r w 3 2 Reserved 0 r 5 4 Select clock source for signal LCCB_SYSCLK_OUT_A 00 LCCB_SYSCLK_IN_A 01 LCCB_SYSCLK_IN_B 10 LCCB_FPETH_RCLK1 11...

Page 186: ...ce List Number Name Description 0 LCCB_SYSCLK_IN_A CLK2A from backplane 1 LCCB_SYSCLK_IN_B CLK2B from backplane 2 LCCB_FPETH_RCLK1 Recovered PHY clock 1 3 LCCB_FPETH_RCLK2 Recovered PHY clock 2 4 LCCB_FRSYNC Clock FRSYNC from ACS8525 5 7 Reserved Table 6 60 Telecom Clock Monitor Control Register Address 0x61 Bit Description Default Access 4 0 Enable supervised Telecom Clock 0 to 4 Set correspondin...

Page 187: ...Mode Corresponding bit is set when the number of positive Clock edges within the selected time base is Lower limit or Upper limit Period Mode Corresponding bit is set when the Clock 0 Period within the selected time base is Lower limit or Upper limit Clearing bit triggers new sequence of measurements 0 LPC r w1c 7 5 Reserved 0 r Table 6 63 Telecom Clock Monitor Select Register Address 0x64 Bit Des...

Page 188: ...r 250 us 1 Gate is open for 500 us 2 Gate is open for 1ms 3 Gate is open for 2ms 4 Gate is open for 4ms 5 Gate is open for 8ms 6 Gate is open for 16ms 7 Gate is open for 32ms 8 Gate is open for 64ms 9 Gate is open for 128ms 10 Gate is open for 256ms 11 Gate is open for 512ms 12 Gate is open for 1024ms 13 Gate is open for 2048ms 14 Gate is open for 4096ms 15 Gate is open for 8192ms 16 Gate is open ...

Page 189: ... master clock 5 Period Counter incremented with each 32th master clock 6 Period Counter incremented with each 64th master clock 7 Period Counter incremented with each 128th master clock 8 Period Counter incremented with each 256th master clock 9 and all others Period Counter incremented with each 512th master clock 7 3 Reserved 0 r 7 Measurement Mode 0 Gate Mode Count positive clock edges during o...

Page 190: ...ing one supervised clock period 65535 Overflow Supervised clock to slow for time base Note Only valid when corresponding bit in Table Telecom Clock Monitor Status Register on page 186 is set 0 LPC r Table 6 66 Telecom Clock Monitor Lower Limit Register Address 0x6C 0x6D Bit Description Default Access 15 0 Lower limit for supervised Telecom Clock Used by Table Telecom Clock Monitor Out of Range Reg...

Page 191: ...DC Frequency 0 LPC r w 00 4 120 ns 8 333 MHz 01 8 240 ns 4 166 MHz 10 16 480 ns 2 083 MHz 11 32 960 ns 1 046 MHz 7 0 MII disabled MDC and MDIO are always tristated 1 MII enabled A write to the bit starts an operation 0 LPC r w Table 6 69 MII Management Interface Control and Address Register Address Offset 0x71 Bit Description Default Access 4 0 Internal PHY Switch register address 0 LPC r w 5 Turn...

Page 192: ...ol Bit 0 Start transaction without leading 1 bits Preamble disabled 1 Start transaction with 32 1 bits Preamble enabled 0 r w Table 6 70 MII Management Interface Lower Byte Register Address Offset 0x72 Bit Description Default Access 7 0 Lower Data Byte 0 LPC r w Table 6 71 MII Management Interface Upper Byte Register Address Offset 0x73 Bit Description Default Access 7 0 Upper Data Byte 0 LPC r w ...

Page 193: ... w Table 6 73 IPMC BIOS Communication Register 2 Address Offset 0x7B Bit Description Default Access 7 0 IPMC BIOS Communication bits PWR_GOOD 0 LPC r w IPMC r w Table 6 74 IPMC BIOS Communication Register 3 Address Offset 0x7C Bit Description Default Access 7 0 IPMC BIOS Communication bits PWR_GOOD 0 LPC r w IPMC r w Table 6 75 LPC Scratch Register Address Offset 0x7D Bit Description Default Acces...

Page 194: ...Maps and Registers ATCA 7475 Installation and Use 6806800S38D 194 Table 6 76 IPMC Scratch Register Address Offset 0x7E Bit Description Default Access 7 0 IPMC Scratch bits PWR_GOOD 0 IPMC r w LPC r ...

Page 195: ...eband interface of the Intel CaveCreek in pass through mode is used to transmit receive its terminal characters via the base interface Only a payload baudrate of 9600 baud is supported You can configure the SOL parameters via standard IPMI commands or via an open source tool called ipmitool 7 2 Installing the ipmitool You can download the open source tool ipmitool from http ipmitool sourceforge ne...

Page 196: ...OL Parameters You can configure the following SOL parameters You can use standard IPMI commands or the ipmitool to modify the parameters 7 3 1 Using Standard IPMI Commands This example shows how to setup the SOL configuration parameter with standard IPMI commands Ipmicmd is used on the local IPMC and the IP is configured Table 7 1 SOL Parameters Parameter Description Set LAN Configuration Paramete...

Page 197: ...ameter Set In Progress Commit ipmicmd k f 0 c 1 5 0 2 smi 0 7 3 2 Using ipmitool The example below shows how to setup a LAN configuration parameter for a potential SOL session with ipmitool for base 0 channel 5 n0s70 ipmitool lan set 5 ipaddr 172 16 0 221 Setting LAN IP Address to 172 16 0 221 n0s70 The following example shows how to query the LAN parameters that are currently in use for a potenti...

Page 198: ...efault Gateway MAC 00 00 00 00 00 00 RMCP Cipher Suites 1 2 3 3 Cipher Suite Priv Max Not Available root localhost ipmitool lan print 2 Set in Progress Set Complete Auth Type Support Auth Type Enable Callback User Operator Admin OEM IP Address Source Unspecified IP Address 172 17 1 220 Subnet Mask 255 255 0 0 MAC Address 00 00 00 00 00 00 Default Gateway IP 172 17 0 1 Default Gateway MAC 00 00 00 ...

Page 199: ...above are fulfilled 2 Compile and install the ipmitool on your target which is destined for opening the SOL session on the ATCA 7475 For details refer to Installing the ipmitool on page 195 3 Apply an IP address to the ATCA 7475 SOL interface for details refer to Configuring SOL Parameters on page 196 4 If necessary change user and password Default user is soluser and password is solpasswd 5 Confi...

Page 200: ...A 7475 SOL interface ipmitool C 1 I lanplus H 172 16 0 221 U soluser P solpasswd k gkey sol activate For details on the command parameters refer to the ipmitool documentation available on http ipmitool sourceforge net To access BIOS setup screen it is necessary to reset the payload SOL session is only available if the payload is powered on and initialized by the BIOS ...

Page 201: ...provides a Boot Bank Sensor illustrating from which BIOS Boot Bank the boot firmware has been booted earlier For more details see Boot Bank sensor in Table Sensor Data Records on page 251 8 1 2 Fail Safe Logic Failsafe is a mechanism to implement automatic BIOS boot bank crisis recovery It observes the BIOS boot phase to reset the processor and to swap the BIOS boot banks in case of accidental boo...

Page 202: ...recover from many scenarios Missing or defect boot block Firmware image has a bad checksum When the Failsafe logic is triggered as a result of the BMC Watchdog timeout a System Firmware Progress event is logged as follows Sensor Type 0x0F System Firmware Progress Figure 8 1 Failsafe Mechanism ...

Page 203: ...lashes are corrupted and the IPMI Fail Safe is enabled 1 BIOS try to start from Boot Bank A BIOS cannot start and IPMC WDT expired IPMC swap BIOS boot bank to B Increment Fail Safe counter 1 2 BIOS try to start from Boot Bank B BIOS cannot start and IPMC WDT expired IPMC swap BIOS boot bank to A Increment Fail Safe counter 2 3 BIOS try to start from Boot Bank A BIOS cannot start and IPMC WDT expir...

Page 204: ...vices is active and standby is done by the IPMC The FPGA Bank selection is implemented such that swapping the SPI flashes is not in effect immediately To ensure that the backup FPGA bank is loaded FPGA upgrades always can just access the backup bank the payload need to be power cycled Therefore swapping the FPGA bank is possible with the following sequence only 1 Swap the FPGA banks 2 Power cycle ...

Page 205: ...blades providing a system interface Table 9 1 Supported Global IPMI Commands Command NetFn Request Response CMD Comments Get Device ID 0x06 0x07 0x01 Cold Reset 0x06 0x07 0x02 Warm Reset 0x06 0x07 0x03 Get Self Test Results 0x06 0x07 0x04 Get Device GUID 0x06 0x07 0x08 Master Write Read 0x06 0x07 0x52 Only for accessing private I2C buses Table 9 2 Supported System Interface Commands Command NetFn ...

Page 206: ...0x07 0x42 Set User Access 0x06 0x07 0x43 Get User Access 0x06 0x07 0x44 Set User Name 0x06 0x07 0x45 Get User Name 0x06 0x07 0x46 Set User Password 0x06 0x07 0x47 Set User Payload Access 0x06 0x07 0x4C Get User Payload Access 0x06 0x07 0x4D Set Channel Security Keys 0x06 0x07 0x5C Table 9 2 Supported System Interface Commands continued Command NetFn Request Response CMD Table 9 3 Supported Watchdo...

Page 207: ...t Response CMD Get SEL Info 0x0A 0x0B 0x40 Reserve SEL 0x0A 0x0B 0x42 Get SEL Entry 0x0A 0x0B 0x43 Add SEL Entry 0x0A 0x0B 0x44 Clear SEL 0x0A 0x0B 0x47 Get SEL Time 0x0A 0x0B 0x48 Set SEL Time 0x0A 0x0B 0x49 Table 9 5 Supported FRU Inventory Commands Command NetFn Request Response CMD Get FRU Inventory Area Info 0x0A 0x0B 0x10 Read FRU Data 0x0A 0x0B 0x11 Write FRU Data 0x0A 0x0B 0x12 ...

Page 208: ...4 0x05 0x24 Get Sensor Hysteresis 0x04 0x05 0x25 Set Sensor Threshold 0x04 0x05 0x26 Most of the threshold based sensors have fixed thresholds Before using this command check whether threshold setting is supported by using the Get Device SDR command Get Sensor Threshold 0x04 0x05 0x27 Set Sensor Event Enable 0x04 0x05 0x28 Get Sensor Event Enable 0x04 0x05 0x29 Get Sensor Event Status 0x04 0x05 0x...

Page 209: ...r different purposes When using the Get Set System Boot Options commands except for parameter 100 use the response request data fields with the Set Selector and the Block Selector set to 0x00 When using the Get Set System Boot Option for the parameter 100 the Set Selector and the Block Selector have a specific meaning Details are given in System Boot Options Parameter 100 on page 212 for details T...

Page 210: ... FPGA configuration stream load 0 Load configuration stream from default boot flash 1 Load configuration stream from backup boot flash Note The new FPGA configuration stream is loaded into the FPGA at the next power up of the payload Bit 0 Default backup boot flash selection 0 Boot from default boot flash 1 Boot from backup boot flash Note the newly selected boot flash is connected to the payload ...

Page 211: ... Byte Description 1 IPMC POST Type Data 1 Set Selector This is the processor ID for which the boot option is to be set 2 Data 2 IPMC POST Type Selector This parameter is used to specify the IPMC POST Type that the IPMC will execute 0x00 Short POST 0x01 Long POST 0x02 to 0xFF Not used The System Boot Options parameter 97 is non volatile During blade production its data is initialized to 0xFF and it...

Page 212: ...s and executes the boot process accordingly Note that the boot parameters in the IPMC storage area have higher priority than the same boot options which may be configured in the firmware itself for example using the setup menu The storage area is divided into two parts the default area and the user area The user area can be read and written by an IPMI user and by default is the area which the boot...

Page 213: ...setting or reading the System Boot Options parameter 100 On some blades with particular firmware types changing a boot parameter in the firmware setup menu changes the boot parameter in the user area as well if the same parameter is defined both in the user area and the set up menu Details are given below Figure 9 1 System Boot Options Parameter 100 Information Flow Overview Table 9 12 System Boot...

Page 214: ...checksum over the boot parameters data section LSB first For backward compatibility reasons the checksums 0x0000 and 0xFFFF are accepted as valid They indicate that no checksum has been calculated and stored Table 9 13 System Boot Options Parameter 100 SET Command Usage Byte Description Request Data 1 Bit 7 when set to 1 the storage area on the IPMC is locked i e no other software can access it Th...

Page 215: ...ns Parameter 100 GET Command Usage Byte Description Request Data 1 Bit 7 reserved Set to 0 Bits 6 0 must contain the value 100 indicating this OEM system boot option 2 Set Selector 0 User area 1 Default area 3 Block Selector Zero based index of the 16 byte block which you want to read from Index 0 refers to the first block of 16 bytes which includes the first two bytes which indicate the boot para...

Page 216: ...sily determined by the number of previously performed successful read accesses This is supported by HPI for details refer to the System Management Interface Based on HPI B User s Guide related to your system environment When used in the System Boot Options parameter 100 the boot parameters and their values are case sensitive All boot options listed in the following table are set by the BIOS setup ...

Page 217: ...x speed width speed width x4x4x4x4 x4x4x8 x8x4x4 x8 x8 x16 speed auto gen1 gen2 gen3 frontnet_boot Boot from Front Panel Network off on basenet_boot Boot from Base Network off on fabricnet_boot Boot from Fabric Network off on artm_net_boot Boot from ARTM Network off on artm_sas_boot Boot from ARTM SAS device off on com_fc Console flow control off hard soft com_ap Console Redirection after POST on ...

Page 218: ...chnology Direct Cache Access on off ioat0_ns Intel Quickdata Technology DMA No Snoop on off ioat1 IntelQuickdataTechnologyforCPU1 on off ioat1_dma IntelQuickdataTechnologyDMA on off ioat1_dca Intel Quickdata Technology Direct Cache Access on off ioat1_ns Intel Quickdata Technology DMA No Snoop on off vtd Intel IO Virtualization on off vtd_ats Intel IO Virtualization Address Translation Service on ...

Page 219: ...nnn SCSI ID use this when using an SAS array frontnet1 Front Panel Network 1 frontnet2 Front Panel Network 2 basenet1 Base Network 1 basenet2 Base Network 2 rtmnet1 RTM Network 1 fabricnet1 Fabric Network 1 fabricnet2 Fabric Network 2 rtmnet2 RTM Network 2 rtmnet3 RTM Network 3 rtmnet4 RTM Network 4 rtmnet5 RTM Network 5 rtmnet6 RTM Network 6 usbcdrom USB Cdrom usb1cdrom USB Cdrom connected to USB...

Page 220: ...ected to USB 1 usb2hdd USB HDD connected to USB 2 usbartmhdd USB HDD connected to USB on RTM usbfdd USB floppy disk efishell UEFI built in shell Table 9 16 boot_order Devices continued Device Description Table 9 17 Supported LAN Device Commands Command NetFn Request Response CMD Set LAN Configuration Parameters 0x0C 0x0D 0x01 Get LAN Configuration Parameters 0x0C 0x0D 0x02 Set SOL Configuration Pa...

Page 221: ...0x2D 0x04 The blade supports the cold reset and graceful reboot options Get FRU LED Properties 0x2C 0x2D 0x05 Get FRU LED Color Capabilities 0x2C 0x2D 0x06 Set FRU LED State 0x2C 0x2D 0x07 Get FRU LED State 0x2C 0x2D 0x08 Set IPMB State 0x2C 0x2D 0x09 Set FRU Activation Policy 0x2C 0x2D 0x0A Get FRU Activation Policy 0x2C 0x2D 0x0B Set FRU Activation 0x2C 0x2D 0x0C Get Device Locator Record ID 0x2...

Page 222: ...t target upgrade capabilities 0x2C 0x2D 0x2E Get component properties 0x2C 0x2D 0x2F Abort firmware upgrade 0x2C 0x2D 0x30 Initiate upgrade action 0x2C 0x2D 0x31 Upload firmware block 0x2C 0x2D 0x32 Finish firmware upload 0x2C 0x2D 0x33 Get upgrade status 0x2C 0x2D 0x34 Activate firmware 0x2C 0x2D 0x35 Query self test results 0x2C 0x2D 0x36 Query rollback status 0x2C 0x2D 0x37 Initiate manual roll...

Page 223: ...onnector Before sending any of these commands the shelf management software must check whetherthereceivingIPMIcontrollersupportsArtesynEmbeddedTechnologiesspecific IPMIcommandsbyusingtheIPMIcommand GetDeviceID SendingArtesynEmbedded Technologies specific commands to IPMI controllers which do not support these IPMI commands will lead to no or undefined results Proper handling of these commands is r...

Page 224: ...of 0x65 has to be used 3 MSB of Artesyn Embedded Technologies IANA Enterprise number A value of 0x00 has to be used 4 Serial connector type 0 Face plate connector 1 Backplane connector All other values are reserved Note Only the faceplate connector is supported No connector on the RTM available 5 Serial connector instance number A sequential number that starts from 0 6 Serial output selector 0 BIO...

Page 225: ...equest Data of Get Serial Output Command Byte Data Field 1 LSB of Artesyn Embedded Technologies IANA Enterprise number A value of 0xCD has to be used 2 Second byte of Artesyn Embedded Technologies IANA Enterprise number A value of 0x65 has to be used 3 MSB of Artesyn Embedded Technologies IANA Enterprise number A value of 0x00 has to be used 4 Serial connector type 0 Face plate connector 1 Backpla...

Page 226: ...d 1 Completion code 2 LSB of Artesyn Embedded Technologies IANA Enterprise number 3 Second byte of Artesyn Embedded Technologies IANA Enterprise number 4 MSB of Artesyn Embedded Technologies IANA Enterprise number 5 Serial output selector Table 9 24 Feature Configuration Command Command NetFn Request Response CMD Defined in Set Feature Configuration 0x2E 0x2F 1Eh Set Feature Configuration Command ...

Page 227: ...sed 4 Feature Selector For details please see table 3 5 Feature Configuration 00h disabled Feature Selector E0 01h enabled Feature Selector E0 02h FFh reserved 6 Persistency Duration 00h volatile Actual duration depends on implementation 01h FFh reserved Response Data 1 Completion Code Generic plus the following command specific completion codes 80h feature selector not supported 81h feature confi...

Page 228: ...during IPMC runtime Table 9 26 Feature Selector Assignments Feature Selector Description E0h FailSafe Function Enable Disable Table 9 27 Get Feature Configuration Command Byte Data Field Request Data 1 LSBofArtesynIANAEnterpriseNumber AvalueofCDhshallbe used 2 2nd byte of Artesyn IANA Enterprise Number A value of 65h shall be used 3 MSB of Artesyn IANA Enterprise Number A value of 00h shall be use...

Page 229: ...d 4 MSB of Artesyn IANA Enterprise Number A value of 00h shall be used 5 Feature Configuration 00h disabled Feature Selector E0 01h enabled Feature Selector E0 02h C0h reserved C1h enabled and activated Feature Selector E0 C2h FFh reserved 6 Persistency Duration Table 9 27 Get Feature Configuration Command continued Byte Data Field Table 9 28 Pigeon Point Extension Commands Command NetFn Request R...

Page 230: ...242 0x2E 0x2F 0x0B Disable Payload Control Table 9 42 on page 242 0x2E 0x2F 0x0C Reset IPMC Table 9 43 on page 243 0x2E 0x2F 0x0D Hang IPMC Table 9 44 on page 243 0x2E 0x2F 0x0E Graceful Reset Table 9 45 on page 244 0x2E 0x2F 0x11 Get Payload Shutdown Time Out Table 9 46 on page 245 0x2E 0x2F 0x15 Set Payload Shutdown Time Out Table 9 47 on page 246 0x2E 0x2F 0x16 Get Module State Table 9 48 on pa...

Page 231: ... intended for debugging purposes and or operation in a non ATCA environment In standalone mode the carrier IPMC automatically activates and deactivates the on carrier payload and modules whenever it does not violate any carrier limitations Manual standalone Manual standalone mode is equivalent to standalone mode with only one exception carrier IPMC control over the on carrier payload is automatica...

Page 232: ... threshold crossing Bits 2 1 Mode The current IPMC modes are defined as 0 Normal 1 Standalone for a description refer to Table 9 29 2 Manual Standalone for a description refer to Table 9 29 Bit 0 Control If set to 0 the IPMC control over the payload is disabled 6 Bits 4 7 Metallic Bus 2 Events These bits indicate pending Metallic Bus 2 requests arrived from the shelf manager 0 Metallic Bus 2 Query...

Page 233: ...s 0 3 Clock Bus 1 Events These bits indicate pending Clock Bus 1 requests arrived from the shelf manager 0 Clock Bus 1 Query 1 Clock Bus 1 Release 2 Clock Bus 1 Force 3 Clock Bus 1 Free 8 Bits 4 7 Reserved Bits 0 3 Clock Bus 3 Events These bits indicate pending Clock Bus 3 requests arrived from the shelf manager 0 Clock Bus 3 Query 1 Clock Bus 3 Release 2 Clock Bus 3 Force 3 Clock Bus 3 Free Table...

Page 234: ...prise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Interface ID 0 Serial Debug Interface Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 5 Bit 7 Echo On If this bit is set the IPMC enables echo for the given serial interface Bits 6 4 Reserved Bits 3 0 Baud Ra...

Page 235: ...prise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Interface ID 0 Serial Debug Interface 5 Bit 7 Echo On If this bit is set the IPMC enables echo for the given serial interface Bits 6 4 Reserved Bits 3 0 Baud Rate ID The baud rate ID defines the interface baud rate as follows 0 9600 bps 1 19200 bps 2 38400 bps 3 57600 bps unsupported 4 115200 bps unsupporte...

Page 236: ...ble If set to 1 the IPMC provides a trace of IPMB L messages that are arriving to going from the IPMC via IPMB L Bit 6 n a Bit 5 KCS Dump Enable If set to 1 the IPMC provides a trace of KCS messages that are arriving to going from the IPMC via KCS Bit 4 IPMB Dump Enable If set to 1 the IPMC provides a trace of IPMB messages that are arriving to going from the IPMC via IPMB O Bit 3 n a Bit 2 Alert ...

Page 237: ...set to 1 the IPMC provides a trace of KCS messages that are arriving to going from the IPMC via KCS Bit 4 IPMB Dump Enable If set to 1 the IPMC provides a trace of IPMB messages that are arriving to going from the IPMC via IPMB O Bit 3 n a Bit 2 Alert Logging Enable If set to 1 the IPMC outputs important alert messages onto the serial debug interface Bit 1 Low level Error Logging Enable If set to ...

Page 238: ...ta 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 5 Hardware Address Table 9 36 Set Hardware Address Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterpr...

Page 239: ... first byte 2 0A byte 3 40 byte 4 00 Table 9 36 Set Hardware Address Command Description continued Type Byte Data Field Table 9 37 Get Handle Switch Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394...

Page 240: ...94 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Handle Switch Status 0x00 The handle switch is open 0x01 The handle switch is closed 0x02 The handle switch state is read from hardware Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Table 9 39 Get Payload Communication Time Out...

Page 241: ... Communication Time Out Command Description continued Type Byte Data Field Table 9 40 Set Payload Communication Time Out Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Payload Time out Payload communication time out measured in hundreds of milliseconds Thus the payload commu...

Page 242: ...ta 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Table 9 42 Disable Payload Control Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A ...

Page 243: ...B Byte first byte 1 0A byte 2 40 byte 3 00 4 Reset Type Code 0x00 Cold IPMC reset to the current mode 0x01 Cold IPMC reset to the Normal mode 0x02 Cold IPMC reset to the Standalone mode for a description refer to Table 9 29 0x03 ColdIPMCresettotheManualStandalonemode for a description refer to Table 9 29 0x04 Reset the IPMC and enter Upgrade mode Response Data 1 Completion Code 2 4 PPS IANA Privat...

Page 244: ... upon receiving the Graceful Reset command or time out If the IPMC participation is necessary the payload must request the IPMC to perform a payload reset The Graceful Reset command is also used to notify the IPMC about the completion of the payload shutdown sequence 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Table 9 44 Hang ...

Page 245: ...IPMC over the payload Interface to notify the IPMC that the payload shutdown is complete Toavoiddeadlocksthatmayoccurifthepayloadsoftwaredoesnotrespond theIPMCprovides a special time out for the payload shutdown sequence If the payload does not send the Graceful Reset command within a definite period of time the IPMC assumes that the payload shutdown sequence is finished and resets the payload Tab...

Page 246: ...rise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 5 Time Out measured in hundreds of milliseconds LSB first Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Table 9 48 Get Module State Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private ...

Page 247: ... is disabled 1 Management power is enabled Bit 3 0 Management power is bad 1 Management power is good Bit 4 0 Payload power is disabled 1 Payload power is enabled Bit 5 0 Payload power is bad 1 Payload power is good Bit 6 0 IPMB L buffer is not attached 1 IPMB L buffer is attached Bit 7 0 IPMB L buffer is not ready 1 IPMB L buffer is ready Table 9 48 Get Module State Command Description continued ...

Page 248: ...equest Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Module Site ID Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Table 9 50 Disable Module Site Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private E...

Page 249: ... the carrier SDR repository Table 9 51 Reset Carrier SDR Repository Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 ...

Page 250: ...Supported IPMI Commands ATCA 7475 Installation and Use 6806800S38D 250 ...

Page 251: ...lade variant r Board serial number Defined by Artesyn Embedded Technologies r Board part number Defined by Artesyn Embedded Technologies r Product info area Product manufacturer EMERSON r Product name Product name of the specific blade variant r Product serial number Defined by Artesyn Embedded Technologies r Product part number Defined by Artesyn Embedded Technologies r Multi record info area Bla...

Page 252: ... Write as 2h 2 1 Record Length 3 1 Record Checksum zero checksum 4 1 Header Checksum zero checksum 5 1 LSB of Manufacturer ID Write as CDh 6 1 Second Byte of Manufacturer ID Write as 65h 7 1 MSB of Manufacturer ID Write as 00h 8 1 Motorola Record ID 01h for Artesyn ECC MAC Address Record 9 1 Record Format Version 01h for this specification 10 1 Number of MAC Address Descriptors N 11 N 9 Artesyn EC...

Page 253: ...B least significant bit first Table 10 4 Interface Type Assignments Interface Type Description 01h ATCA Base Interface 02h ATCA Fabric Interface 03h Front Rear Panel 04h Mezzanine Module 05h Serial over LAN SOL 06h Fibre Channel WWPN 07h AMC MicroTCA Common Options Region 08h AMC MicroTCA Fat Pipe Region 09h AMC MicroTCA Extended Fat Pipe Region 10h ATCA Update Channel 11h Multi type Base Fabric a...

Page 254: ... change Number of power draw levels 1 The amount of possible power levels Early Power Draw Levels Watt Complete early power level including IPMC Steady state Power Draw Levels Watt 1 8 GHz 8x4GB DDR3 RTM Max 260 Watts Complete steady power consumption including IPMC Transition from early to steady levels sec 0s Table 10 6 IPMI Sensors Overview Sensor Number Sensor Name Sensor Type Description 0 Ho...

Page 255: ...ds on page 260 11 1 0V Voltage 0x02 Refer Table Sensor Data Records on page 260 12 VCC CPU0 Voltage 0x02 Refer Table Sensor Data Records on page 260 13 1 5V DDR3 Voltage 0x02 Refer Table Sensor Data Records on page 260 14 Bottom Edge Temp Temp 0x01 Refer Table Sensor Data Records on page 260 15 Top Edge Temp Temp 0x01 Refer Table Sensor Data Records on page 260 16 IPMC POST Management Subsystem He...

Page 256: ...e 0x25 Refer Table Sensor Data Records on page 260 27 BIOS POST code OEM 0xD1 Refer Table Sensor Data Records on page 260 28 Reset Source OEM 0xDA Refer Table Sensor Data Records on page 260 29 IPMC temp Temp 0x01 Refer Table Sensor Data Records on page 260 30 ACC temp Temp 0x01 Refer Table Sensor Data Records on page 260 31 CPU Status Processor 0x07 Refer Table Sensor Data Records on page 260 32 ...

Page 257: ... 3 OEM 0xE2 Refer Table Sensor Data Records on page 260 43 CPLD Pwr Fail 4 OEM 0xE3 Refer Table Sensor Data Records on page 260 44 CPU0 temp Temp 0x01 Refer Table Sensor Data Records on page 260 45 CPU1 temp Temp 0x01 Refer Table Sensor Data Records on page 260 46 PCH temp Temp 0x01 Refer Table Sensor Data Records on page 260 47 DDR 1 temp Temp 0x01 Refer Table Sensor Data Records on page 260 48 D...

Page 258: ... 52 DDR 6 temp Temp 0x01 Refer Table Sensor Data Records on page 260 53 DDR 7 temp Temp 0x01 Refer Table Sensor Data Records on page 260 54 DDR 8 temp Temp 0x01 Refer Table Sensor Data Records on page 260 Table 10 6 IPMI Sensors Overview Sensor Number Sensor Name Sensor Type Description ...

Page 259: ...rmation and Sensor Data Records ATCA 7475 Installation and Use 6806800S38D 259 The following figure shows the locations of all temperature sensors available on board Figure 10 1 Location of Temperature Sensors ...

Page 260: ...rete 0x6F 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 7 4 Cause 3 0 Previous State FRU ID 0x0 M0 0x1 M1 0x2 M2 0x3 M3 0x4 M4 0x5 M5 0x6 M6 0x7 M7 Asrt Auto 1 ACC Module Hot Swap 0xF0 Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 7 4 Cause 3 0 Previous State FRU ID 0x0 M0 0x1 M1 0x2 M2 0x3 M3 0x4 M4 0x5 M5 0x6 M6 0x7 M7 Asrt Auto 2 Hotswap_RTM Hot Swap 0xF0 Sensor specific discrete 0x6F 0x0 0x1...

Page 261: ...Asrt Deass Auto 7 3 3V Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 8 3 3V Mgmt Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 9 1 8V Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 10 1 2V Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 11 1 0V Voltage 0x02 Threshold 0x01 reading th...

Page 262: ...irmware Progress Asrt Auto 19 OS Boot OS Boot 0x1F Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0xFF 0xFF 0x0 A boot completed 0x1 C boot completed 0x2 PXE boot completed 0x3 Diagnostic boot completed 0x4 CD_ROM boot completed 0x5 ROM boot completed 0x6 boot completed Asrt Auto 20 Boot Error Boot Error 0x1E Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 0x4 0xFF 0xFF 0x0 No Bootable me...

Page 263: ...RR 0x5 PCI SERR Asrt Auto 24 Battery Battery 0x29 Sensor specific discrete 0x6F 0x1 0xFF 0xFF 0x1 Battery failed Asrt Auto 25 ATCA 7475 IPMC OEM 0xD5 Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 0x4 0x5 0x0 Watchdog Reset 0x1 Software Reset 0x2 Power Failure 0x3 Hard Boot 0x4 Cold Boot 0x5 Warm Boot Asrt Auto 26 Power Good Entity Presence 0x25 Sensor specific discrete 0x6F 0x0 0x1 0xFF 0xFF 0x0 E...

Page 264: ...Sensor specific discrete 0x6F 0x1 0xFF 0xFF 0x1 Thermal Trip Asrt Auto 32 48v A Volts Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 33 48v B Volts Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 34 48v Amps Current 0x03 Threshold 0x01 reading threshold No Thresholds Asrt Deass Auto 35 HoldUp Cap Volts Voltage 0x02 Threshold 0x01 reading thr...

Page 265: ...ply Failure detected Asrt Deass Auto 39 48V B Supply Power Supply 0x08 Sensor specific discrete 0x6F 0x0 0x1 See IPMI Spec 0xFF 0x0 Presence detected 0x1 Power Supply Failure detected Asrt Deass Auto 40 CPLDPwrFail1 OEM 0xE0 Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x0 12V Power Good 0x1 5 0V 3 0V Power Good 0x2 1 8V 1 0V Power Good PCH 0x3 1 0V Power Good Mgmt 0x4 1 2V 2 5V Power...

Page 266: ...0 0x5 0x6 0x7 0x0 FPGA Done 0x5 ACC Power Good Present 0x6 ACC Module Present 0x7 ACC Module Power Good Asrt Auto 44 CPU0 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 45 CPU1 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 46 PCH temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 47 DDR 1 temp Temp 0x01 Threshold 0x01...

Page 267: ...ld 0x01 reading threshold unr uc unc Asrt Deass Auto 53 DDR 7 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 54 DDR 8 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto Table 10 7 Sensor Data Records continued Sensor Number Sensor Name Sensor Type Event Reading Type Event Data Byte 1 Event Data Byte 2 Event Data Byte 3 Event Threshold Description...

Page 268: ...FRU Information and Sensor Data Records ATCA 7475 Installation and Use 6806800S38D 268 ...

Page 269: ...sh For update it is recommended to use the Pigeon Point System modified Ipmitool 11 1 2 Installing the Ipmitool procedure 1 Get the Pigeon Point System Ipmitool from the package Ipmitool 1 8 9 pps 7 tgz 2 Extract the source code Prompt tar xzvf Ipmitool 1 8 9 pps version tgz 3 Go to the directory where you have extracted the Ipmitool Prompt cd path Ipmitool 1 8 9 pps version 4 Build the Ipmitool P...

Page 270: ...ce is the fastest HPM 1 upgrade The images and the Ipmi tool need to be on the payload to be upgraded Example Prompt ipmitool hpm upgrade file 11 1 3 2 IPMB 0 This interface represents the backplane IPMI bus and allows remote firmware upgrade The count of the simultaneous upgrades is limited because of the bus speed Example from shelf manger Prompt ipmitool t 0x92 hpm upgrade file Example with RMC...

Page 271: ...oot either of two redundant copies of the firmware in the flash depending on the current value of the special partition status byte that is stored in the internal IPMC EEPROM The boot loader can fall back to the backup copy by booting the alternate partition The boot loader manages two firmware partitions the active and backup partition It is responsible for detecting if the active firmware is inv...

Page 272: ...obepossible This leads to the fact that an automatic boot bank switching via the IPMC is not possible which is a requirement for HPM 1 to activate Payload always has access to the active boot bank and the IPMC always has access to the inactive boot bank All HPM 1 commands are directed to the inactive boot bank this includes get component properties The following figure shows the connection of the ...

Page 273: ...ected programming interface A power cycle is required after the BIOS FPGA update 11 4 Upgrade Package The HPM upgrade package for this release contains the following files Figure 11 2 SPI Busses Connection Table 11 1 HPM Upgrade Package Filename Description 9806822J10P_atca 747x ipmc all hpm HPM compatible upgrade image of the IPMC firmware and the Boot Loader ...

Page 274: ...0P_atca 747x ipmc fw hpm HPM compatible upgrade image of the IPMC firmware atca 747x bios 2 1 6 hpm HPM file contains the version 2 1 6 BIOS image atca747x_rev08 bin hpm HPM file contains the version 0 08 FPGA image Ipmitool 1 8 9 pps 7 tgz PPS modified Ipmitool necessary for HPM upgrades on ATCA747x Table 11 1 HPM Upgrade Package continued Filename Description ...

Page 275: ...n and Use 6806800S38D 275 A Replacing the Battery A 1 Replacing the Battery Some blade variants contain an on board battery Its location is shown in the following figure A battery less variant based on SUPERCAP is available on demand ...

Page 276: ...Replacing the Battery ATCA 7475 Installation and Use 6806800S38D 276 Figure A 1 Location of On board Battery ...

Page 277: ...Data Loss If the battery does not provide enough power anymore the RTC is initialized and the data in the NVRAM is lost Therefore replace the battery before seven years of actual battery use have elapsed Data Loss Replacing the battery always results in data loss of the devices which use the battery as power backup Therefore back up affected data before replacing the battery Data Loss If installin...

Page 278: ...attery proceed as follows 1 Remove battery 2 Install the new battery following the positive and negative signs PCB and Battery Holder Damage Removing the battery with a screw driver may damage the PCB or the battery holder To prevent this damage do not use a screw driver to remove the battery from its holder ...

Page 279: ...or released products you can also visit our Web site for the latest copies of our product documentation 1 Go to www artesyn com computing 2 Under SUPPORT click TECHNICAL DOCUMENTATION 3 Under FILTER OPTIONS click the Document types drop down list box to select the type of document you are looking for 4 In the Search text box type the product name and click GO Table B 1 Artesyn Embedded Technologie...

Page 280: ...ormation is subject to change without notice Table B 2 Manufacturer s Documents Company Document Title Intel 6300ESB I O Controller Data sheet 82546EB GB Gigabit Ethernet Controller Documentation 6700PXH 64 bit PCI to PCI bridge Data sheet E7520 Memory Controller Data sheet IPMI V1 5 Specifications Intel XeonTM Processor Technical Documents LSI Logic LSIFC929XL Dual Channel PCI X to Fibre Channel ...

Page 281: ......

Page 282: ...esyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies Inc All other product or service names are the property of their respective owners 2014 Artesyn Embedded Technologies Inc ...

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