Artesyn ATCA-7475, Installation And Use Manual

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Maps and Registers
ATCA-7475 Installation and Use (6806800S38D)
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6.3.1 Register Decoding
The FPGA registers can be accessed from the host or the IPMC. For the host access, LPC bus
interface is used. The IPMC uses an SPI interface.
6.3.1.1 LPC Decoding
The LPC bus supports different protocols.
<reset>: 0 or 1 Default value after deassertion of the reset signal <reset>
Ext. External Reset Source. Default depends on external logic level.
Table 6-5 Register Access Type
Access Description
r Read only
w Write only
r/w Read and write
w1c Write-1-to-clear, ignore bit while reading
r/w1c Read and write-1-to-clear, write 0 has no effect
r/w1s Read and write-1-to-set, write 0 has no effect
r/w1t Read and write-1-to-toggle, write 0 has no effect
LPC: The prefix "LPC:" signals that the access is restricted to the LPC interface.
For example, LPC: r/w means that the register bit is readable/writable from the LPC
interface
IPMC: The prefix "IPMC:" signals that the access is restricted to the IPMC SPI interface.
For example, IPMC: r/w means that the register bit is readable/writable from IPMC SPI
interface
Table 6-4 Register Default (continued)
Default Description