Cyclone 10 LP RefKit User Guide
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Page | 56
February 2022
5.2.11
Adding Timing Constraints
Timing Constraints tell the Quartus what the timing requirements for this design are. Timing
Constraints are required in every CPLD/FPGA design.
5.2.11.1
To add the timing constraints, select
File
→
New
and under the
“
Other File
”
section,
select
“
Synopsys Design Constraints File
”
and select
“
OK
”
5.2.11.2
Type or copy the following lines into this new file:
#create input clock which is 12MHz
create_clock
-name
CLK12M
-period
83.333
[
get_ports
{
CLK12M
}]
#derive PLL clocks
derive_pll_clocks
#derive clock uncertainty
derive_clock_uncertainty
#set false path
set_false_path
-from
[
get_ports
{
USER_BTN
}]
set_false_path
-from
*
-to
[
get_ports
{
LED
*}]
The first line
“create cl c ”
tells Quartus Prime that the clock, CLK12M is 83.333 ns
(12 MHz). It also assigns the CLK12M to a pin (port) in the .sdc format.
The second line
“ eri e pll cl c s”
tells the software to look if there are any PLLs, and
if so, automatically derive the clock multiplication/division of the outputs of the PLL even
if they are used internally within the CPLD/FPGA.
The third line
“ eri e cl c uncertainty”
tells the software to automatically determine
the internal clock uncertainty. No clock is ideal, and thus there will be some internal jitter
within the FPGA associated with it.
e f urt an fift line “set false pat ”
tells the software to not do any timing
optimization to the stated paths/pins. The I/Os of this design are trivial, so they can be
ignored in the Timing Analysis.