Arrow Cyclone 10 LP RefKit, User Manual, Page: 14 / 75

Cyclone 10 LP RefKit User Guide www.arrow.com
Page | 14 February 2022
Board Reference FPGA Pin No. Pin Func. Description I/O Std
BDBUS0 PIN_C20 Bidir D[0] of bidirectional data bus 3.3 V
BDBUS1 PIN_B21 Bidir D[1] of bidirectional data bus 3.3 V
BDBUS2 PIN_B22 Bidir D[2] of bidirectional data bus 3.3 V
BDBUS3 PIN_C21 Bidir D[3] of bidirectional data bus 3.3 V
BDBUS4 PIN_C22 Bidir D[4] of bidirectional data bus 3.3 V
BDBUS5 PIN_D21 Bidir D[5] of bidirectional data bus 3.3 V
BDBUS6 PIN_D22 Bidir D[6] of bidirectional data bus 3.3 V
BDBUS7 PIN_E21 Bidir D[7] of bidirectional data bus 3.3 V
BCBUS0 PIN_E22 Bidir D[0] of bidirectional data bus 3.3 V
BCBUS1 PIN_F21 Bidir D[1] of bidirectional data bus 3.3 V
BCBUS2 PIN_F22 Bidir D[2] of bidirectional data bus 3.3 V
BCBUS3 PIN_H21 Bidir D[3] of bidirectional data bus 3.3 V
BCBUS4 PIN_H22 Bidir D[4] of bidirectional data bus 3.3 V
BCBUS5 PIN_J21 Bidir D[5] of bidirectional data bus 3.3 V
BCBUS6 PIN_J21 Bidir D[6] of bidirectional data bus 3.3 V
BCBUS7 PIN_J19 Bidir D[7] of bidirectional data bus 3.3 V
3.3.2 Fast Ethernet
The board has two independent 10/100Mbps Ethernet ports with RJ-45 connectors. For the
physical layer, the Microchip KSZ8081 Ethernet PHY is used, which is suitable for general
applications.
The MAC-to-PHY interface is configured to a MII interface connections with MDIO interface as
management.
Board Reference FPGA Pin No. Pin Func. Description I/O Std
ETH1_MDIO PIN_AA21 Bidir Management Interface Data 3.3 V
ETH1_MDC PIN_AA22 Output Management Interface Clock 3.3 V
ETH1_COL PIN_T19 Bidir MII Collision Detect 3.3 V
ETH1_CRS PIN_R20 Bidir MII Carrier Sense 3.3 V
Et ernet
Et ernet
E DI
E II
E DI
E II
Figure 8 – MAC-to-PHY connection