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reducing and/or eliminating wait state (IOCHRDY) conditions.

•  All status registers are properly latched as well to prevent change in values during a bus read cycle.

•  I/O Read line is digitally filtered to support noisy bus problems and eliminate the possibility of dropped analog input data.

•  Indexed register array banked over the 8254 registers. This opens the door for many new functions as described above.

•  Moving average filter has been corrected to present channel data in the proper order.

Update as of January 15, 2008 (Revision 090115H)

•  8254 Counter/Timer is also available within the indexed register set. This allows software access to all registers when the 

indexed register set is enabled.

Please  note  that  all  of  the  new  registers  are  designed  such  that  if  they  are  not  configured,  everything  defaults  to  the  classic
modes  of  operation.  Thus,  existing  software  will  function  without  modification.  Writing  values  to  the  new  registers  enhances
operations.

3.2

 Photo 

3.2 Photo

STX104 Reference Manual

Copyright © 2009 by 

Apex Embedded Systems

. All rights reserved.

Thursday, October 08, 2009

7

3

Summary of Contents for STX104

Page 1: ......

Page 2: ...t Resolution Apex Embedded Systems 116 Owen Road Monona WI 53716 Phone 608 256 0767 Fax 608 256 0765 www apexembeddedsystems com customer service apexembeddedsystems com Copyright Notice Copyright 2009 by Apex Embedded Systems All rights reserved ...

Page 3: ...initions 15 ADC Sample 15 ADC Burst 15 Analog Input Sample Event 15 Frame 15 Intra Sample 15 Analog Inputs 17 Calibration 17 Connectivity 18 Single Ended 18 Differential 19 Data Acquisition Modes 22 Classic DAS16jr 16 22 Classic DAS1602 23 STX104 Reference Manual Copyright 2009 by Apex Embedded Systems All rights reserved Thursday October 08 2009 iii ...

Page 4: ...vity 35 Hardware Configuration 37 Base Address Table 37 Compatibility Selection and Extended Functions 38 CPU Limitation Accommodations 39 Register Set 41 Summary 41 Software Strobe Offset 0 44 ADC Data LSB Offset 0 45 ADC Data MSB Offset 1 45 ADC Data Offset 0 45 ADC Channel Offset 2 50 Digital Outputs Offset 3 52 Digital Inputs Offset 3 53 DAC Channel A LSB Offset 4 54 STX104 Reference Manual Co...

Page 5: ... 70 RB 1 71 8254 Configuration Offset 15 RB 0 Index 71 RB 1 72 FIFO Status LSB Offset 15 74 Index Data LSB Offset 12 RB 1 74 Index Data MSB Offset 13 RB 1 75 Index Data Offset 12 RB 1 75 Index Pointer Offset 14 RB 1 76 Conversion Disable Offset 1028 Index 64 RB 1 78 Burst Mode Enable Offset 1029 Index 65 RB 1 79 Burst Function Enable Offset 1030 Index 66 RB 1 80 Extended Status Offset 1031 Index 6...

Page 6: ...alog Input Frame Counter Index 48 RB 1 100 Miscellaneous Output Configuration Register Index 208 RB 1 101 FIFO Data Available Index 224 RB 1 103 FIFO Configuration Index 228 RB 1 104 Scratch Pad Index 248 RB 1 105 Board ID Index 250 RB 1 105 Power Supply 107 Interrupt Summary 109 Connector Summary 111 Mechanicals 115 Revision Information 117 Support Policy 119 General Support Policy 119 Recommende...

Page 7: ...Specifications 121 Ordering Information 123 Index a STX104 Reference Manual Copyright 2009 by Apex Embedded Systems All rights reserved Thursday October 08 2009 vii ...

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Page 9: ...bedded Systems Continuous improvement policy utilizes customer feedback to improve existing products and create new product offerings based on needs of our customers Continued Success Apex Embedded Systems 1 STX104 Reference Manual Copyright 2009 by Apex Embedded Systems All rights reserved Thursday October 08 2009 1 1 ...

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Page 11: ...have been subject to misuse including static discharge neglect accident or modification or which have been soldered or altered during assembly and are not capable of being tested DO NOT USE PRODUCTS SOLD BY APEX EMBEDDED SYSTEMS AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS Products sold by Apex Embedded Systems are not authorized for use as critical components in life support devices ...

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Page 13: ...U to read in blocks of ADC data from FIFO further increasing bandwidth and reducing complexity Burst mode with only one interrupt generated per complete scan thus reducing interrupt overhead and increasing effective throughput One interrupt per 512 samples is possible in FIFO mode On board LED to indicate that the STX104 is being addressed By observing the LED you can quickly determine system acti...

Page 14: ...er see page 97 with resolution to 25 nanoseconds for improved timing between samples in ADC burst mode Non synchronization synchronization with trigger start see page 93 In other words sample timing can remain at fixed intervals regardless of triggering start event or be synchronized to the triggering start event respectively 32 bit frame timer see page 95 with resolution 25 nanoseconds ADC Burst ...

Page 15: ...ed to present channel data in the proper order Update as of January 15 2008 Revision 090115H 8254 Counter Timer is also available within the indexed register set This allows software access to all registers when the indexed register set is enabled Please note that all of the new registers are designed such that if they are not configured everything defaults to the classic modes of operation Thus e...

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Page 17: ...esses known board related issues and includes methods to work around the issues Description none end 4 STX104 Reference Manual Copyright 2009 by Apex Embedded Systems All rights reserved Thursday October 08 2009 9 4 ...

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Page 19: ...discharge static electricity from yourself by touching a grounded conductor such as your computer chassis your computer must be turned off Whenever you handle a board hold it by the edges and avoid touching any board components or cable connectors 5 STX104 Reference Manual Copyright 2009 by Apex Embedded Systems All rights reserved Thursday October 08 2009 11 5 ...

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Page 21: ...d damage Helpful hint During system prototyping install the spacers to help guide installation and provide another means of checking board alignment We recommend having the bolt end of the spacer facing up to act as a guide or alignment pin 6 STX104 Reference Manual Copyright 2009 by Apex Embedded Systems All rights reserved Thursday October 08 2009 13 6 ...

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Page 23: ...ut Sample Event Analog Input Sample Event is a signal that causes either an analog input sample or analog input burst depending on how the STX104 is set up 7 4 Frame A Frame is a generalized term This is the record that is deposited per frame time into the FIFO memory Currently a frame is the equivalent to an ADC Burst in terms of the amount of samples stored in the FIFO 7 5 Intra Sample Intra sam...

Page 24: ...See Also Analog Input Burst Timer see page 97 STX104 Reference Manual 7 5 Intra Sample Copyright 2009 by Apex Embedded Systems All rights reserved 16 Thursday October 08 2009 7 ...

Page 25: ...8 installed short J7 pin 36 to J7 pin 37 effectively connecting the single ended input to analog ground In the case of differential inputs jumper J8 not installed short J7 pin 35 and pin 36 to J7 pin 37 effectively connecting the differential input to analog ground 2 While performing ADC conversions and reading the ADC value adjust potentiometer ADC_OFFSET R4 until the nearest zero value can be ac...

Page 26: ... Amplifier Bias Currents The primary path of amplifier bias currents is the AGND or common and since the source is tied to AGND amplifier bias currents flow through the sensor to AGND Amplifier bias currents are typically on the order of tens of nano amps Source Resistance Source resistance Rsource along with cable and input parasitic capacitances must be taken into considered to determine Single ...

Page 27: ...ng and lower cost Disadvantages Since all inputs are referred to AGND i e common the possibility exists for ground loops or voltage drops along common connections which will add to noise or measurement errors 8 2 2 Differential Full differential analog inputs Description A differential analog input channel consists of two inputs high side positive and low side negative The output measured is the d...

Page 28: ...as value could be as low as zero ohms but using zero ohms you are reverting to single ended behavior Source Resistance Source resistance Rsource along with cable and input parasitic capacitances must be taken into considered to determine minimum settling time More details can be found here see page 97 Input Ranges The input ranges for each half of the differential input along with the full differe...

Page 29: ...tric at the outputs and thus nulled at the output If the negative side of the source driving the bridge is tied to the system supply that supplies power to the STX104 then the Rbias is not required because input bias currents have a complete DC path If you are not sure whether your signal source is referenced to the STX104 AGND power down the system and using an ohmmeter measure the resistance bet...

Page 30: ...ing starts and stops can originate from internal or external events Interrupt subsystem Variety of interrupts can be generated based on both internal and external events Moving average filter 8 3 1 Classic DAS16jr 16 Single ADC sample per analog input sample event Analog input sampling events enhanced from 3 to 13 possible sources Supports DMA see note Description The DAS16jr 16 mode is the simple...

Page 31: ...iming between ADC samples within a burst are adjustable from 5 microseconds to 53 seconds to 25 nanosecond resolution Analog input sampling events enhanced from 3 to 13 possible sources Large FIFO depth allows for greater interrupt latency or readout latency Supports DMA see note Description The DAS1602 mode is a step up from the DAS16jr 16 mode in that this mode additionally supports ADC bursting...

Page 32: ...h Speed Sampling CPU read out N blocks of data per unit of time i e CPU burst reads Sample timing and intra sample timing in ADC burst modes adjustable to 25 nanosecond resolution FIFO interrupt generated interrupts and events are very flexible and support optimal CPU bursting ultimately dependent on other CPU overhead or rhythmic behavior such as flash drives Data fragment buffer reduces PC 104 g...

Page 33: ... stop sampling Repeat sequence Large FIFO depth offers ability to collect large groups of data with a post readout scheme Description The most generalized sampling scheme is illustrated below 8 3 Data Acquisition Modes STX104 Reference Manual Start Stop Trigger Encased Frame Groups Copyright 2009 by Apex Embedded Systems All rights reserved Thursday October 08 2009 25 8 ...

Page 34: ...mpling when N samples Frames reached i e Stop Trigger event Large FIFO depth offers set it and forget it methodology thus drastically reducing CPU software monitoring overhead Description N Sample Collection STX104 Reference Manual 8 3 Data Acquisition Modes Copyright 2009 by Apex Embedded Systems All rights reserved 26 Thursday October 08 2009 8 ...

Page 35: ...unctions within the example code below will compute and configure the proper analog input timing registers based on firmware revision level If only 8254 timers are used then resolution is fixed to 1uSec In the case of using the Analog Input Frame Timer see page 95 and the Analog Input Burst Timer see page 97 resolution is improved to 25 nanoseconds When using the triggering subystem to synchronize...

Page 36: ...settling time is eleven RC time constants ai_time_intra_sample_ns AIBT_Register_Value 25 nSec 5000 nSec AIBT_Register_Value ai_time_intra_sample_ns 25 nSec 200 c The minimum frame time will be minimum_ai_time_frame_ns last_channel first_channel 1 ai_time_intra_sample_ns d The frame time can now be computed ai_time_frame_ns AIFT_Register_Value 1 25 nSec AIFT_Register_Value ai_time_frame_ns 25 nSec ...

Page 37: ...low_count 1 while high_count 2L high_count high_count 1 low_count low_count 1 set counter timer 2 outportb stx104_base_address board STX104_CT_CONFIGURATION 0xB4 octet unsigned int high_count 0x00FF outp stx104_base_address board STX104_CT2_DATA octet octet unsigned int high_count 8 outp stx104_base_address board STX104_CT2_DATA octet set counter timer 1 outportb stx104_base_address board STX104_C...

Page 38: ..._AI_Timing_8254_Set board ai_time_intra_sample_ns outp stx104_base_address board STX104_BURST_FUNCTION 0x00 outp stx104_base_address board STX104_BURST_MODE_ENABLE 0x00 outp stx104_base_address board STX104_CONVERSION_DISABLE 0x00 else utilize adc burst mode STX104_AI_Timing_8254_Set board ai_time_frame_ns outp stx104_base_address board STX104_BURST_FUNCTION 0x40 outp stx104_base_address board STX...

Page 39: ... Stop Trigger Source event What is the purpose of the triggering subsystem It allows precise control as to when analog input sampling can occur It is possible to synchronize sampling to 60Hz line source or whatever is chosen It is possible to configure the STX104 to trigger on an event and accumulate N samples and then stop sampling Synchronization of Analog Input Frame Timer to Trigger Start SAIF...

Page 40: ...ogether and divided by sixteen average of sixteen ADC samples It is important to recognize that after the filter is reset or at the beginning of data sampling that it may require at least 16 data samples per channel be taken until the data becomes current In other words there is an inherent 16 sample delay in the ADC data that is read out of the ADC Data Register 8 7 CPU Readout Methods 8 7 1 DMA ...

Page 41: ...ou are in DAS1602 mode jumper M0 is installed receiving a terminal count will set the Conversion Disable bit to false thus disabling any additional ADC sampling Writing 0x00 to the Conversion Disable Register see page 78 will allow ADC sampling to continue In order to use DMA you must set up the computer s DMA controller and page registers before enabling DMA on the STX104 board We consider DMA a ...

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Page 43: ...age 55 2 Adjust potentiometer DA1_G R2 until the desired full scale is reached Calibration of DAC Channel B 1 Write 65535 0xFFFF to Register DAC Channel B see page 57 2 Adjust potentiometer DA2_G R1 until the desired full scale is reached 9 2 Connectivity Description Each DAC channel is a single ended type output We suggest wiring the return path back to one of the AGND pins at connector J7 9 2 Co...

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Page 45: ...1 0 0 0 1 0 0x0240 0x240 1 0 0 1 0 0 0x0250 0x250 1 0 0 1 0 1 0x0260 0x260 1 0 0 1 1 0 0x0280 0x280 1 0 1 0 0 0 0x0290 0x290 1 0 1 0 0 1 0x02A0 0x2A0 1 0 1 0 1 0 0x02B0 0x2B0 1 0 1 0 1 1 0x02C0 0x2C0 1 0 1 1 0 0 0x02D0 0x2D0 1 0 1 1 0 1 0x02E0 0x2E0 1 0 1 1 1 0 0x02F0 0x2F0 1 0 1 1 1 1 0x0300 0x300 1 1 0 0 0 0 0x0310 0x310 1 1 0 0 0 1 0x0320 0x320 1 1 0 0 1 0 0x0330 0x330 1 1 0 0 1 1 0x0340 0x340 ...

Page 46: ... supports 8 bit or 16 bit systems XT or AT respectively The enhanced register set now supports redirection of the DAS1602 extended burst registers to the indexed array register set thus allowing more addressing and data width options including both XT and AT compatibility Jumper position M0 selects one of these compatibility modes The DAS1602 compatibility offers ADC sample see page 15 and ADC bur...

Page 47: ...les It is important to recognize that after the filter is reset or at the beginning of data sampling that it may require at least 16 data samples per channel be taken until the data becomes current In other words there is an inherent 16 sample delay in the ADC data that is read out of the ADC Data Register MODE M4 M3 M2 M1 M0 10 Bit Address Decode A15 to A10 ignored DAS1602 burst registers availab...

Page 48: ...ding 8 or 16 bit PC 104 data bus without or with 40 pin connector respectively STX104 Reference Manual 10 3 CPU Limitation Accommodations Copyright 2009 by Apex Embedded Systems All rights reserved 40 Thursday October 08 2009 10 ...

Page 49: ... X DAC Channel B LSB see page 57 dacbl BYTE w 6 X DAC Channel B MSB see page 57 dacbh BYTE w 7 X DAC Channel B see page 57 dacb WORD w 6 X Clear Interrupts see page 59 cir BYTE w 8 X ADC Status see page 60 4 asr BYTE r 8 X ADC Control see page 62 4 acr BYTE rw 9 X Pacer Clock Control see page 64 pccr BYTE w 10 X FIFO Status MSB see page 65 2 4 fsh BYTE r 10 X ADC Configuration see page 68 4 acfg B...

Page 50: ...er Start Delay see page 92 5 tsd DWORD rw 20 1 Analog Input Section Analog Input General Configuration see page 93 5 aigc BYTE rw 32 1 Analog Input Frame Timer see page 95 5 aift DWORD rw 36 1 Analog Input Burst Timer see page 97 5 aibt DWORD rw 40 1 Analog Input Frame Maximum see page 99 5 aifm DWORD rw 44 1 Analog Input Frame Counter see page 100 5 aifc DWORD r 48 1 DAS1602 Redirected Registers ...

Page 51: ...ne STX104_DIGITAL_OUTPUTS 3 define STX104_DIGITAL_INPUTS 3 define STX104_DAC_CHANA_LSB 4 define STX104_DAC_CHANA_MSB 5 define STX104_DAC_CHANA 4 define STX104_DAC_CHANB_LSB 6 define STX104_DAC_CHANB_MSB 7 define STX104_DAC_CHANB DACB 6 define STX104_CLEAR_INTERRUPTS 8 define STX104_ADC_STATUS 8 define STX104_ADC_CONTROL 9 define STX104_PACER_CLOCK_CONTROL 10 define STX104_FIFO_FLAGS 10 define STX1...

Page 52: ...X104_CT0_DATA_INDEXED 68 define STX104_CT1_DATA_INDEXED 69 define STX104_CT2_DATA_INDEXED 70 define STX104_CT_CONFIGURATION_INDEXED 71 define STX104_MISCELLANEOUS_OUTPUT_CONFIG 208 define STX104_FIFO_DATA_AVAILABLE 224 define STX104_FIFO_CONFIGURATION 228 define STX104_SCRATCH_PAD 248 define STX104_BOARD_ID 250 11 2 Software Strobe Offset 0 Software Strobe Register Expanded version of the ADC Soft...

Page 53: ...ADC Sample or ADC Burst See Also Register Summary see page 41 Example 11 3 ADC Data LSB Offset 0 ADC Data LSB Please refer to ADC Data see page 45 Register for further details See Also Register Summary see page 41 11 4 ADC Data MSB Offset 1 ADC Data MSB Please refer to ADC Data see page 45 Register for further details See Also Register Summary see page 41 11 5 ADC Data Offset 0 ADC Data Register 1...

Page 54: ... between the STX104 and CPU PC 104 ISA bus can be doubled by simply reading the ADC register as a 16 bit register Software examples are shown below Further improvement in bus bandwidth can be had by limiting the CPU burst readouts i e Insw function to the data fragment buffer size thus eliminating I O wait states When FIFO Superset is enabled M1 jumper installed the ADC data is read out of the FIF...

Page 55: ...ng REP INSW alleviates video problems related with DMA as well as improved CPU timing management i e DMA adds timing holes in the system that are not easily managed by simple real time kernels The speed of any ISA bus I O transaction is dependent on the CPU ISA bus speed which is usually set in the BIOS setup use this setting with caution as it may affect performance of other cards and or can caus...

Page 56: ...ck fifo status adc_value channel inpw base_address 0 16 Bit Read with FIFO enabled in C C using REP INSW typedef unsigned int WORD void insw WORD port void buf int count _ES FP_SEG buf Segment of buf _DI FP_OFF buf Offset of buf _CX count Number to read _DX port Port asm REP INSW void main WORD data 512 insw 0x300 data 512 assumes 512 samples or two blocks in FIFO An example shown below illustrati...

Page 57: ...hannel zero only base address set to factory default at 0x300 initialize STX104 outportb 0x309 0x00 no interrupts no DMA and s w trigger Applies to firmware revision 080214H only for non zero first_channel please write to channel register twice to correct for errata issue This is transparent for other firmware revisions simply means that acquisition controller is reset twice outportb 0x302 channel...

Page 58: ... FC 3 0 rw 0000 First Channel This is the first analog channel that is sampled When this value is written it will also set the current channel CH FC LC 3 0 rw 0000 Last Channel This is the last analog channel that is sampled Once this channel has been sampled the current channel value will wrap to the first channel value Description The channel register contains first channel and the last channel ...

Page 59: ...er M0 is installed ACQUISITION CONTROLLER RESET Writing to the Channel Register resets the internal acquisition controller in all modes MOVING AVERAGE FILTER RESET Writing to the Channel Register also resets the internal moving average filter in all modes when jumper M3 is installed The CNV bit see ADC Status Register see page 60 will become active for approximately six microseconds while the movi...

Page 60: ...16 Channel Single Ended 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 8 Channel Differential see page 19 6 7 0 1 2 3 4 5 6 7 0 1 2 11 7 Digital Outputs Offset 3 Digital Output Register Register Layout Offset 0x3 Byte 0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X DOUT3 DOUT2 DOUT1 DOUT0 Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION X Don t Care DOUT 3 0 w 0000 Digital Outputs These bits are write only Non inv...

Page 61: ...mpatibility mode These bits are set to zero for DAS16jr 16 mode These bits are set to one for DAS1602 mode compatibility X Don t Care DIN 3 0 r 0000 Digital Inputs DIN0 also functions as an ADC external trigger input As a trigger input it is deglitched by an internal match filter and requires a minimum pulse width of no less than 200nS See the Interrupt Summary see page 41 section for further func...

Page 62: ... DIN0 J7 12 TTL Input Description Digital TTL inputs See Also Register Summary see page 41 Example 11 9 DAC Channel A LSB Offset 4 DAC Channel A LSB Please Refer to DAC Channel A see page 55 Register Details See Also Register Summary see page 41 11 10 DAC Channel A MSB Offset 5 DAC Channel A MSB Please Refer to DAC Channel A see page 55 Register Details See Also Register Summary see page 41 STX104...

Page 63: ... is updated once the MSB is written Writing only the MSB will update the DAC channel output The results of changing jumper settings at J5 will only take affect after writing the MSB on the DAC output The two 8 bit DAC registers can be written simultaneously by writing the data as a 16 bit I O transaction Examples out dx ax or outpw base_address 4 dac_value DAC outputs are available in either DAS16...

Page 64: ...ed See Also Register Summary see page 41 Example Examples of how to write to the DAC output register in 16 bit DAC mode 8 Bit Writes in C C unsigned int dac_value outp base_address 4 dac_value 0xFF outp base_address 5 dac_value 8 or union unsigned int word unsigned char byte 2 dac_value outp base_address 4 dac_value byte 0 outp base_address 5 dac_value byte 1 16 Bit Write in C C unsigned int dac_v...

Page 65: ...Layout DAC Channel B LSB Offset 0x6 Byte 0 Offset 0x6 Word 0 D7 D6 D5 D4 D3 D2 D1 D0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DAC Channel B MSB Offset 0x7 Byte 0 Offset 0x6 Word 0 D15 D14 D13 D12 D11 D10 D9 D8 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION DB 15 0 w na DAC Channel A data word in 16 Bit mode DA0 is the least significant bit and DB15 is the most sign...

Page 66: ...t legacy operation or full 16 bit DAC mode POWER UP or RESET At power up or reset the DAC outputs are at set to zero volts OUTPUT VOLTAGE CONVERSION OUTPUT RANGE DB1_UB J5 DB1_R J5 RESOLUTION NEG FULL SCALE VOLTAGE POS FULL SCALE VOLTAGE NEG FULL SCALE HEX POS FULL SCALE HEX 10 Volts 1 1 305 uV 10 00 10 00 0x0000 0xFFFF 5 Volts 1 0 153 uV 5 000 5 000 0x0000 0xFFFF 0 10 Volts 0 1 153 uV 0 000 10 00...

Page 67: ... 15 Clear Interrupts Offset 8 Clear Interrupt Register Register Layout Offset 0x8 Byte 0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION X Don t Care Description Writing to this register will clear any pending interrupts 11 15 Clear Interrupts Offset 8 STX104 Reference Manual Copyright 2009 by Apex Embedded Systems All rights reserved Thursday October 08 ...

Page 68: ...ter may cause the CNV bit to become active indicating that a STX104 internal reset is in progress typically less than 1uS and less than 10uS when moving average filter is enabled 1 ADC conversion scan or acquisition reset in progress 0 ADC Idle default UB r Unipolar Bipolar ADC input mode setting J9 0 bipolar Measure both negative and positive input voltages J9 not stuffed 1 unipolar Measure only ...

Page 69: ...This is the channel currently selected on the board and is the channel that will be used for the next ADC conversion provided CNV 0 unless a new value is written to the channel register The CH 3 0 will change shortly after an ADC trigger TAS r 0 Trigger Activity State This is the same status bit as the TRG bit found in the ADC Configuration see page 68 Register The trigger status is provided here ...

Page 70: ...is used to replace the term trigger since triggering takes on a more generalized definition Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION IES 3 0 rw 0000 Interrupt enhanced select available only in Enhanced Register Set Mode 0000 Not valid interrupts disabled default 0001 Not valid interrupts disabled 0010 IRQ9 2 IRQ2 for 8 bit or XT IRQ9 for 16 bit or AT 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IR...

Page 71: ... We strongly encourage you to use the REP INSW instruction or Insw function in Linux as it performs better than DMA and is substantially simpler to set up and use Note that DMA performs I O to memory transfers a byte at a time DMA 1 and DMA 3 are byte wide transfers while REP INSW performs I O to memory transfers a word at a time If you are designing a real time system you will have better timing ...

Page 72: ...yte 0 DAS16jr 16 Compatibility Mode M0 jumper not installed D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X CT_SRC0 GCTRL Offset 0xA Byte 0 DAS1602 Compatibility Mode M0 jumper installed D7 D6 D5 D4 D3 D2 D1 D0 ABL3 ABL2 ABL1 ABL0 X X CT_SRC0 GCTRL Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION ABL 3 0 w ADC Burst Length Determines the number of conversions per trigger when in burst mode One to sixteen sa...

Page 73: ...with no gating 1 Counters 1 and 2 are gated by DIN0 J7 12 DIN0 is connected to a 10K ohm pull up resistor X Don t Care Description See Also Register Summary see page 41 Example 11 19 FIFO Status MSB Offset 10 FIFO Status MSB Register Register Layout Offset 0xA Byte 0 FIFO Status MSB Register D7 D6 D5 D4 D3 D2 D1 D0 FIFO_INT DFR a FF FE FBR11 FBR10 FBR9 FBR8 Offset 0xF Byte 0 FIFO Status LSB Regist...

Page 74: ...mples at a time 1 block When FBR 0 use a software loop that monitors the FE bit while reading in the samples until the FIFO is empty Description The FIFO Status Registers are only available when FIFO Superset is Enabled M1 jumper installed The number of data blocks used in order to generate a FIFO interrupt FIFO_INT can be adjusted via the FIBLK 1 0 bits in the Interrupt Source Select see page 83 ...

Page 75: ...AX FIFO STATUS Revision History 15JAN07 read FIFO status twice to remove the possibility of reading an incorrect value due to FIFO status changing during a 25nSec interval define STX104_FIFO_STATUS_READ_COUNT_MAX 1 void STX104_FIFO_Status int board union unsigned int value unsigned char octet 2 ff_stat STX104_FIFO_STATUS_READ_COUNT_MAX 1 unsigned int fbr_blocks unsigned int fbr_blocks_minimum unsi...

Page 76: ...ess board STX104_FIFO_FLAGS stx104_fifo_status_blocks board ff_stat value 0x0FFF if ff_stat value 0x1000 0x0000 stx104_fifo_status_empty board true else stx104_fifo_status_empty board false if ff_stat value 0x2000 0x0000 stx104_fifo_status_full board true else stx104_fifo_status_full board false 11 20 ADC Configuration Offset 11 ADC Configuration Register Register Layout Offset 0xB Byte 0 Write On...

Page 77: ...unavailable 0 trigger inactive default 1 trigger active ADBU r depends on J9 ADC bipolar unipolar 0 bipolar setting jumper J9 not installed 1 unipolar setting GAIN 1 0 rw 00 ADC gain setting 00 gain of x1 default 01 gain of x2 10 gain of x4 11 gain of x8 X Don t care Description REGISTER BANK SELECT Register Bank Select is a mechanism for providing additional configuration options for the STX104 w...

Page 78: ...hanging from one bank to another Recommend only changing the bank when one read writes to the 8254 since that is likely to be read written to the least amount compared to the indexed register array Alternatively one could check the RB bit each time an indexed register is read or written it will then take longer on average to read write registers void STX104_Set_Bank int board char bank unsigned ch...

Page 79: ...e 72 Register for further details See Also Register Summary see page 41 11 22 8254 CT1 Data Offset 13 RB 0 Index 69 RB 1 8254 CT1 Data Register Please refer to the 8254 Configuration see page 72 Register for further details See Also Register Summary see page 41 11 23 8254 CT2 Data Offset 14 RB 0 Index 70 RB 1 8254 CT2 Data Register Please refer to the 8254 Configuration see page 72 Register for fu...

Page 80: ...2 D1 D0 CT1D7 CT1D6 CT1D5 CT1D4 CT1D3 CT1D2 CT1D1 CT1D0 Offset 0xE RB 0 8254 Counter Timer Two Data Register D7 D6 D5 D4 D3 D2 D1 D0 CT2D7 CT2D6 CT2D5 CT2D4 CT2D3 CT2D2 CT2D1 CT2D0 Offset 0xF RB 0 8254 Counter Timer Configuration Register D7 D6 D5 D4 D3 D2 D1 D0 SC1 SC0 RW1 RW0 M2 M1 M0 BCD Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION CT0D 7 0 rw 8254 Counter Timer Zero Data Register CT1D 7 ...

Page 81: ...101 Mode 5 Hardware triggered strobe retriggerable BCD w Binary Coded Decimal BCD Counter 4 decades if set to one otherwise 16 bit binary counter Description This register is available when Register Bank Status is 0 see ADC Configuration see page 68 Register bit RB See Also Register Summary see page 41 ADC Configuration Register see page 68 8254 Data Sheet Example ANALOG INPUT 8254 COUNTER 1 2 TIM...

Page 82: ...BUG_MODE fprintf stdout CT2 HB u n octet endif set counter timer 1 outportb stx104_base_address board STX104_CT_CONFIGURATION 0x74 octet unsigned int low_count 0x00FF outp stx104_base_address board STX104_CT1_DATA octet ifdef STX104_DEBUG_MODE fprintf stdout CT1 LB u n octet endif octet unsigned int low_count 8 outp stx104_base_address board STX104_CT1_DATA octet ifdef STX104_DEBUG_MODE fprintf st...

Page 83: ...Register Layout Offset 12 Byte 0 Offset 12 Word 0 RB 1 D7 D6 D5 D4 D3 D2 D1 D0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Offset 13 Byte 1 Offset 12 Word 0 RB 1 D15 D14 D13 D12 D11 D10 D9 D8 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION ID 15 0 rw Indexed Data Description See Also Register Summary see page 41 11 28 Index Data Offset 12 RB 1 STX104 Reference Manual C...

Page 84: ...r Description The drawing below illustrates the ISA bus interface to the indexed register array Index Register Description The Index Register is an address pointer that points into the register set array The Index Register can address any byte or word Read or writing any data within the indexed array will cause the Index Register to automatically increment if AIID 0 refer to General Configuration ...

Page 85: ...Data_Byte int board unsigned char index unsigned char value outp stx104_base_address board STX104_INDEX_POINTER index value unsigned char inp stx104_base_address board STX104_INDEX_DATA return value INDEXED ARRAY DATA WORD READ static unsigned int STX104_Read_Indexed_Data_Word int board unsigned char index unsigned int value outp stx104_base_address board STX104_INDEX_POINTER index value inpw stx1...

Page 86: ... Conversion Disable Offset 1028 Index 64 RB 1 Conversion Disable Register DAS1602 Compatible Configuration Register In 10 bit address decode mode the DAS1602 compatible registers are also accessible through the indexed register set Register Layout Offset 0x404 RB X Also located at Index 0x40 Byte 0 RB 1 D7 D6 D5 D4 D3 D2 D1 D0 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 Bit Definitions NAME DIRECTION DEFAULT ...

Page 87: ...Register Layout Offset 0x405 RB X Also located at Index 0x41 Byte 0 RB 1 D7 D6 D5 D4 D3 D2 D1 D0 ABME7 ABME6 ABME5 ABME4 ABME3 ABME2 ABME1 ABME0 Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION ABME 7 0 w 0x00 ADC Burst Mode Enable Register On power up or reset the ADC burst mode is disabled This register is only available if FE bit is true DAS1602 Functions are enabled Writing a 0x00 to this re...

Page 88: ...ction disabled DAS1602 Function Enable Register On power up or reset the DAS1602 functions are disabled Writing 0x40 6410 to this register enables the DAS1602 functions Writing a 0x00 to this register disables DAS1602 functions Description DAS1602 Function Enable Register On power up or reset the DAS1602 functions are disabled Writing 0x40 6410 to this register enables the DAS1602 functions Writin...

Page 89: ...ME r 0 ADC Burst Mode Enabled 0 disabled default 1 enabled FE r 0 DAS1602 Function Enabled 0 disabled DAS16jr 16 functionality only default 1 enabled CD r 1 Conversions Allowed 0 ADC Conversions Disabled 1 ADC Conversions Allowed default WS r 0 Wait States This bit is always zero for no wait states CLK r J6 1MHz Jumper Counter Timer clock source 0 1MHz selected based on jumper 1MHz 1 10MHz selecte...

Page 90: ...per Mode jumper DMA state at connector J6 0 Jumper is not installed 1 Jumper is installed M4J r J6 M4 jumper Mode jumper M4 state at connector J6 0 Jumper is not installed 1 Jumper is installed M3J r J6 M3 jumper Mode jumper M3 state at connector J6 0 Jumper is not installed 1 Jumper is installed M2J r J6 M2 jumper Mode jumper M2 state at connector J6 0 Jumper is not installed 1 Jumper is installe...

Page 91: ...000 none default 0001 Reserved 0010 Interrupt Threshold see page 86 Counter 0011 Analog Input Frame Maximum see page 99 0100 Trigger Start and transition to active trigger state 0101 Trigger Stop and transition to inactive trigger state 0110 none 0111 none 1000 DIN0 rising edge 1001 DIN0 falling edge 1010 DIN1 rising edge 1011 DIN1 falling edge 1100 DIN2 rising edge 1101 DIN2 falling edge 1110 DIN...

Page 92: ...1 DIN0 falling edge 1010 DIN1 rising edge 1011 DIN1 falling edge 1100 DIN2 rising edge 1101 DIN2 falling edge 1110 DIN3 rising edge 1111 DIN3 falling edge Description See Also Register Summary see page 41 Example 11 36 Interrupt Configuration Index 4 RB 1 Interrupt Source Select Register Register Layout Index 0x04 Byte 0 Word 0 RB 1 D7 D6 D5 D4 D3 D2 D1 D0 X X X X FIBLK3 FIBLK2 FIBLK1 FIBLK0 Index...

Page 93: ... function Use alternate interrupt generation to achieve desired interrupts ITS 3 0 rw 0000 Interrupt Threshold Counter Source Select Increment by 0000 none default 0001 Sample or Frame see page 15 i e ADC burst 0010 Block i e 256 samples 0011 Analog Input Maximum Frame see page 15 Count 0100 Trigger Start and transition to active trigger state 0101 Trigger Stop and transition to inactive trigger s...

Page 94: ...512 Blocks or 131 072 Samples 1001 1024 Blocks or 262 144 Samples 1010 2048 Blocks or 524 288 Samples 1011 0 0625 Block or 16 Samples 1100 0 125 Block or 32 Samples 1101 0 25 Block or 64 Samples 1110 0 5 Block or 128 Samples 1111 1 Block or 256 Samples X Don t Care Description See Also Register Summary see page 41 Example 11 37 Interrupt Threshold Index 8 RB 1 Interrupt Threshold Register Register...

Page 95: ...Threshold Source Counter Select refer to the Interrupt Source Select see page 83 Register is reached an output is generated which can subsequently be used to generate an interrupt or be used to cause an ADC sample or ADC burst depending on configurations It is possible for this counter to be used as a form of an event pre scalar for ADC sampling or ADC bursting or interrupt generation One time Int...

Page 96: ...ting default 1 Inverted DOP3 rw 0 Digital Output DOUT3 J7 5 Polarity 0 Non inverting default 1 Inverted DOP2 rw 0 Digital Output DOUT2 J7 6 Polarity 0 Non inverting default 1 Inverted DOP1 rw 0 Digital Output DOUT1 J7 7 Polarity 0 Non inverting default 1 Inverted DOP0 rw 0 Digital Output DOUT0 J7 8 Polarity 0 Non inverting default 1 Inverted X Don t Care Description The Digital Output Configuratio...

Page 97: ... rw 0 Swap DIN1 and DIN3 0 Classic mode DIN1 wired to J7 11 and DIN3 to J7 9 to support existing customers 1 Normal mode DIN1 wired to J7 9 and DIN3 to J7 11 DIP3 rw 0 DIN3 J7 9 Polarity 0 Non inverting default 1 Inverted DIP2 rw 0 DIN2 J7 10 Polarity 0 Non inverting default 1 Inverted DIP1 rw 0 DIN1 J7 11 Polarity 0 Non inverting default 1 Inverted DIP0 rw 0 DIN0 J7 12 Polarity 0 Non inverting de...

Page 98: ...Byte 1 Index 0x10 Word 0 RB 1 D15 D14 D13 D12 D11 D10 D9 D8 TEN X STM1 STM0 TSS3 TSS2 TSS1 TSS0 Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION X Don t Care TEN rw 0 Trigger Enable 0 disabled default 1 enabled STM 1 0 rw 00 Start Trigger Mode 00 trigger source default 01 trigger followed by trigger delay 10 trigger followed by sync followed by trigger delay 11 Reserved STX104 Reference Manual 1...

Page 99: ...e 1111 DIN3 falling edge ETS 3 0 rw 0000 End Stop Trigger Source 0000 none default 0001 writing 0xAA to the software strobe register 0010 Analog Input Frame see page 15 Maximum 0011 Analog Input Sample Frame see page 15 Timer 0100 8254 Counter 0 Output CT_OUT0 rising edge 0101 8254 Counter 0 Output CT_OUT0 falling edge 0110 8254 Counter 2 Output CT_OUT2 rising edge 0111 8254 Counter 2 Output CT_OU...

Page 100: ... rising edge 1111 DIN3 falling edge Description Configures the trigger section for a variety of ADC data collection start and stop situations See Also Register Summary see page 41 Example 11 41 Trigger Start Delay Index 20 RB 1 Trigger Start Delay Register Range is 0 to 53 68 Seconds in steps of 25 nanoseconds Register Layout Index 0x14 Byte 0 Index 0x14 Word 0 RB 1 D7 D6 D5 D4 D3 D2 D1 D0 TSD7 TS...

Page 101: ...ription The actual delay interval is calculated as Delay_nanoseconds 25 TSD Where 0 TSD 2147483648 Thus the trigger start delay is adjustable from 0 nSec to 53 68 Seconds Range 0 to 53 68 Seconds Resolution 25 nanoseconds See Also Register Summary see page 41 Example 11 42 Analog Input General Configuration Index 32 RB 1 Analog Input General Configuration Register 11 42 Analog Input General Config...

Page 102: ...n also moves the first sample to just after the trigger start rather than sampling at any time i e 0 to 1 sample interval after the trigger start 0 disabled default Timing between samples remains fixed regardless of point of trigger 1 Clear Analog Input Frame see page 15 Timer upon Trigger Start Sampling begins just after the trigger start thus synchronizing the sampling to the trigger start SAIFC...

Page 103: ...escription The Analog Input General Configuration Register configures the source of ADC sampling or ADC burst signalling in legacy terms it is the old ADC triggering sources Upon reset or power up it defaults to legacy mode of operation See Also Register Summary see page 41 Example 11 43 Analog Input Frame Timer Index 36 RB 1 Analog Input Frame see page 15 Timer Register Range is 5 uSec to 53 68 S...

Page 104: ... DEFAULT DESCRIPTION AIFT 31 0 rw 0x00000000 Description The actual time interval is calculated as ai_time_frame_ns AIFT 1 25 nSec Where 0 AIFT 2147483648 Anything below 5 uSec will be limited by the intra sample timing which is limited to 5 uSec at a minimum Thus the ADC frame time is adjustable from 5 microseconds to 53 68 seconds in 25 nanosecond steps Range 5 uSec to 53 68 Seconds Resolution 2...

Page 105: ...23 AIBT22 AIBT21 AIBT20 AIBT19 AIBT18 AIBT17 AIBT16 Index 0x2B Byte 3 Index 0x2A Word 1 RB 1 D31 D30 D29 D28 D27 D26 D25 D24 AIBT31 AIBT30 AIBT29 AIBT28 AIBT27 AIBT26 AIBT25 AIBT24 Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION AIBT 31 0 rw 0x00000000 Description Adjusts the time between ADC samples in a ADC Burst mode i e the intra sample time In legacy mode this is 5 microseconds The actual ...

Page 106: ... more specifically settling time Differential see page 19 inputs have 47pF input capacitance and single ended inputs have 27pF input capacitance we tend to lean on the high side or worse case So to keep signal settle times to less than 1 LSB requires Rmax settle_time Cin bits_resolution ln 2 4uS 47pF 16 ln 2 7674 ohms You will want to keep the devices driving the STX104 inputs with source impedanc...

Page 107: ...to 2 147 483 648 Frames Register Layout Index 0x2C Byte 0 Index 0x2C Word 0 RB 1 D7 D6 D5 D4 D3 D2 D1 D0 AIFM7 AIFM6 AIFM5 AIFM4 AIFM3 AIFM2 AIFM1 AIFM0 Index 0x2D Byte 1 Index 0x2C Word 0 RB 1 D15 D14 D13 D12 D11 D10 D9 D8 AIFM15 AIFM14 AIFM13 AIFM12 AIFM11 AIFM10 AIFM9 AIFM8 Index 0x2E Byte 2 Index 0x2E Word 1 RB 1 D23 D22 D21 D20 D19 D18 D17 D16 AIFM23 AIFM22 AIFM21 AIFM20 AIFM19 AIFM18 AIFM17 ...

Page 108: ... see page 15 Count Maximum Range 1 AIFM 2147483648 Range 0 to 2147483648 Frames Resolution 1 Frame see page 15 Counting every ADC sample at 5 microsecond sample rate the maximum can be set to just under 3 hours Counting every ADC Burst at 50uSec ADC Burst 20KHz the maximum can be set to just under 29 hours See Also Register Summary see page 41 Example 11 46 Analog Input Frame Counter Index 48 RB 1...

Page 109: ...5 AIFC24 Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION AIFC r 0x00000000 Analog Input Frame see page 15 Count Description The Analog Input Frame see page 15 Count Register indicates the actual number of samples when ADC set for non ADC bursting mode of operation or the number of frames when ADC set for ADC burst mode of operation See Also Register Summary see page 41 Example 11 47 Miscellaneo...

Page 110: ... 15 Timer 101 Interrupt Counter Increment 110 zero 111 IOCHRDY CTOUT0PE rw 0 CT_OUT0 J7 3 pulse extender 0 disabled default 1 enabled extend selected signal by 100nSec approximately CTOUT0SEL 2 0 rw 000 CT_OUT0 J7 3 source select 000 8254 CT0 output default 001 Digital Output DOUT4 Reference Digital Outputs see page 52 Register 010 Trigger delay end pulse 011 Trigger delay start pulse 100 Interrup...

Page 111: ...ex 0xE2 Word 1 RB 1 D23 D22 D21 D20 D19 D18 D17 D16 FDA23 FDA22 FDA21 FDA20 FDA19 FDA18 FDA17 FDA16 Index 0xE3 Byte 3 Index 0xE2 Word 1 RB 1 D31 D30 D29 D28 D27 D26 D25 D24 FDA31 FDA30 FDA29 FDA28 FDA27 FDA26 FDA25 FDA24 Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION FDA r 0x00000000 FIFO Data Available Number of analog input samples that remain in the FIFO Description The number of 16 bit wor...

Page 112: ... the High Speed CPU FIFO Buffer can reduce bus wait states generated due to waiting for STX104 main memory data availability In many cases bus wait states due to IOCHRDY are eliminated We found that overall throughput through the ISA bus was improved by approximately 15 By default the CPU FIFO Buffer is disabled in order to maintain classic timing characteristics which might be critical to a custo...

Page 113: ...Definitions NAME DIRECTION DEFAULT DESCRIPTION SCR 15 0 rw 0x0000 Scratch Pad Register Description Can be used for temporarily storing a previous state Also used to verify ISA bus interface See Also Register Summary see page 41 Example 11 51 Board ID Index 250 RB 1 Board Identification Register Register Layout Index 0xFA Byte 0 Index 0xFA Word 0 RB 1 11 51 Board ID Index 250 RB 1 STX104 Reference ...

Page 114: ...ID8 Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION BID 15 0 r Board ID 0x1008 Revision 080214 14FEB08 and Revision 080407H 07APR08 Board ID 0x1009 Revision 090115 15JAN09 Description See Also Register Summary see page 41 Example STX104 Reference Manual 11 51 Board ID Index 250 RB 1 Copyright 2009 by Apex Embedded Systems All rights reserved 106 Thursday October 08 2009 11 ...

Page 115: ...5V supply line The 5V at J7 pin 15 is derived from the on board DC DC converter and on board regulator Recommend that the 5V be returned via one of the AGND pins at J7 Recommend that the 5V be returned via the DGND for larger currents If 5V is going to drive a small analog load 50mA then it is OK to return via AGND pins at J7 12 STX104 Reference Manual Copyright 2009 by Apex Embedded Systems All r...

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Page 117: ... now configurable refer to the Interrupt Configuration see page 84 Register 1 X 1 1 Interrupt generated when a DMA terminal count is received from the DMA controller to indicate completion of the DMA transfer 0 1 0 1 Interrupt generated when 512 additional samples are deposited in the FIFO Write to the Clear Interrupt Register to clear the interrupt The number of blocks required to generate an int...

Page 118: ...GCTRL bit is set this can be used to detect the beginning of pacer clock gating i e start of a group of samples Writing to the Clear Interrupt Register will also clear the INT bit ADDITIONAL INTERRUPT CONFIGURATIONS AND SOURCES Please reference the following registers listed for detailed information In summary additional IRQ selection IRQ sources along with programmable interrupt threshold count i...

Page 119: ...y Description STX104 I O Connector J7 Name Notes CT_OUT0 CT_CLK0 CT_OUT2 TRIG DIN0 DIN1 CT_GATE0 DIN2 14 STX104 Reference Manual Copyright 2009 by Apex Embedded Systems All rights reserved Thursday October 08 2009 111 14 ...

Page 120: ... Function 0 Bipolar Analog Inputs values accepted 1 Unipolar Analog Inputs values only Factory Default Note 1 Jumper installed 0 Jumper not installed DIFFERENTIAL OR SINGLE ENDED ANALOG INPUT J8 Jumper Function 0 Differential see page 19 Inputs 8 channels 1 Single Ended Inputs 16 channels Factory Default STX104 Reference Manual 14 Copyright 2009 by Apex Embedded Systems All rights reserved 112 Thu...

Page 121: ... to 10 Volts Factory Default Note 1 Jumper installed 0 Jumper not installed DA2_UB DA2_R DAC 2 RANGE 0 0 0 to 5 Volts 0 1 0 to 10 Volts 1 0 5 to 5 Volts 1 1 10 to 10 Volts Factory Default Note 1 Jumper installed 0 Jumper not installed 14 STX104 Reference Manual Copyright 2009 by Apex Embedded Systems All rights reserved Thursday October 08 2009 113 14 ...

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Page 123: ...lli inches or mils Y milli inches or mils Lower Left Mounting Hole 200 200 Lower Right Mounting Hole 3350 200 Upper Left Mounting Hole 350 3575 Upper Right Mounting Hole 3250 3575 J7 pin 1 3300 3200 15 STX104 Reference Manual Copyright 2009 by Apex Embedded Systems All rights reserved Thursday October 08 2009 115 15 ...

Page 124: ...STX104 Reference Manual 15 Copyright 2009 by Apex Embedded Systems All rights reserved 116 Thursday October 08 2009 15 ...

Page 125: ...ge to the board ID 2 Revision 090115H added mapping the 8254 registers through the index register set to improve accessibility by driver software Example STX104 Revision Information define STX104_REVISION_071604 0 define STX104_REVISION_080214 0x1008 define STX104_REVISION_080407 0x1008 define STX104_REVISION_090115 0x1009 REVISION DETECTION static unsigned int STX104_Revision_Detected int board u...

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Page 127: ...tems support asp Contact us via email at customer service apexembeddedsystems com Technical support related inquiry answered typically within a 24 hour period 17 3 Need Custom Modifications Contact us for customization or modifications to our standard product If you need large quantities we can generally save you money through optimizing card designs to meet your exact needs 17 3 Need Custom Modif...

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Page 129: ...typical DC Drift or Zero Drift 2ppm oC 1 5ppm oC typical Input Bias Current 50nA maximum Absolute Maximum Input Voltage 35V Common Mode Voltage Range 10V Common Mode Rejection Ratio 70dB at 60Hz Integral Linearity Error 1 5 LSB 3 LSB on 1 25V range Differential see page 19 Linearity 1 LSB Accuracy 0 003 of reading 1 LSB Gain Drift 7ppm C Trigger Sources Programmable internal 32 bit counter timer e...

Page 130: ...x Counter Timers Analog Input Pacer Timer 32 bit Analog Input Frame see page 15 Timer or legacy 32 bit down counter 2 82C54 counters cascaded Clock Source Jumper selectable 40MHz 25nS or legacy 1 MHz or 10 MHz on board clock source jumper select for 8254 General Purpose 16 bit down counter 1 82C54 counter Interrupt DMA Trigger End of analog input conversion General Operating temperature range 40 t...

Page 131: ...og I O Module with 1M sample FIFO without dual 16 bit DAC SKU STX104 1MFIFO DAQ NODAC For the latest drivers and technical support please contact us at customer service apexembeddedsystems com Product documentation can be found on our website at http www apexembeddedsystems com documentation asp 19 STX104 Reference Manual Copyright 2009 by Apex Embedded Systems All rights reserved Thursday October...

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Page 133: ... Enable Offset 1030 Index 66 RB 1 80 Burst Mode Enable Offset 1029 Index 65 RB 1 79 Burst Read 33 C Calibration 17 35 Classic DAS1602 23 Classic DAS16jr 16 22 Clear Interrupts Offset 8 59 Compatibility Selection and Extended Functions 38 Connectivity 18 35 Connector Summary 111 Continuous High Speed Sampling 24 Conversion Disable Offset 1028 Index 64 RB 1 78 CPU Limitation Accommodations 39 CPU Re...

Page 134: ...cellaneous Output Configuration Register Index 208 RB 1 101 Moving Average Filter 32 N Need Custom Modifications 119 N Sample Collection 26 O Ordering Information 123 P Pacer Clock Control Offset 10 64 PC 104 Insertion Caution 13 Photo 7 Power Supply 107 R Recommended Sequence in Obtaining Customer Support 119 Register Set 41 Revision Information 117 S Scratch Pad Index 248 RB 1 105 Single Read 33...

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