Analog Devices ADZS-BF707-BLIP2, Manual

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ADZS-ADSP-BF707-BLIP2 Board Evaluation System Manual I-1
I INDEX
A
ADSP-BF707 processor, x
architecture, of this BLIP2 board, 2-2
audio interface, 1-9
B
bill of materials, A-1
BLIP2 board installation, 1-3
BLIP2 board session startup, 1-4
board schematic (ADZS-BF707-BLIP2), B-1
C
configuration, of this BLIP2 board, 1-2
connectors, 2-8
diagram of locations, 2-8 , 2-9
J2 (RF wireless), 2-11
J3 (SD), 2-11
P3 (JTAG/SWD/SWO), 2-10
P4 (USB)), 2-10
P5 (power), 2-11
P8 (USB to UART)), 2-10
contents, of this BLIP2 board package, 1-2
D
DDR3 memory, 1-7
debug interface, 1-9
default configuration, of this BLIP2 board, 1-2
E
EngineerZone, xvi
evaluation license, 1-6
example programs, 1-10
G
GPIO push buttons (SW1 and SW2), 2-5
GPIO Status LED (LED1), 2-7
I
installation, of this BLIP2 board, 1-3
interface
debug, 1-9
SD, 1-9
UART, 1-8
J
JTAG/SWD/SWO connector (P3), 2-10
L
LEDs, 2-6
diagram of locations, 2-6
LED1 (GPIO status), 2-7
LED4 (SYS_FAULT), 2-7
license restrictions, 1-6
N
notation conventions, xvi