"100" when WR2,
"100" when WR3,
"100" when WR4,
"101" when WR_D1,
"111" when ENDW1,
"111" when ENDW2,
"111" when ENDW3,
"111" when ENDW4,
"101" when CS3,
"101" when CS4,
"101" when CS5,
"101" when CS6,
"001" when RD1,
"001" when RD2,
"001" when RD3,
"001" when RD4,
"101" when ENDR1,
"---" when others;
-- *************************************************
-- State/Reset Control
-- *************************************************
state_clocked:process(reset, clk)
begin
if (reset = '1') then
present_state <= IDLE; -- UART State
u_rd_bar <= '1'; -- UART State
u_en_bar <= '1'; -- UART State
u_wr_bar <= '1'; -- UART State
present_wstate <= WAIT0; -- Wait State
elsif rising_edge(clk) then
present_state <= next_state; -- UART State
u_rd_bar <= uart_ctrl_d(2); -- UART State
u_en_bar <= uart_ctrl_d(1); -- UART State
u_wr_bar <= uart_ctrl_d(0); -- UART State
present_wstate <= next_wstate; -- Wait State
end if;
end process state_clocked;
ack <= '1' when (reset = '1') else
(u_ack AND w_ack) when ((u_ack_v = '1')
OR (w_ack_v = '1')) else
'Z'; -- Generate ACK
-- *************************************************
-- EMAFE Control logic
-- *************************************************
-- Control the buffering of data to and from the EMAFE
-- interface
72
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