command as follows: "Opens the Sample Rate dialog that lets you select a sample rate from 7000
to 48000 Hz." The default sample rate is 48000. Do NOT change the sample from this setting. If
you need to change sample rates for your program, you will need to write your own CODEC
driver. Information on doing this is provided in Chapter 3 of the ADSP-21065L EZ-KIT Lite
Evaluation System Manual.
A.1 CPLD File
Listing A-1 shows the Cypress WARP file used to program the CPLD on the board. The CPLD is a
CY7371i-83AC, which is a 32-macrocell CPLD with in-circuit programmability. The functions
performed are:
1. Extends the EPROM read cycles (board silicon revision 0.0 only). The access cycles used by the
ADSP-21065L when booting, are too short for the EPROM; therefore, the CPLD deasserts the
ACK line long enough to extend the cycle to an appropriate time for the EPROM.
2. Translates the read and write cycles into cycles that are appropriate for the UART. The timing
requirements between the chip select, read/write lines, and data accesses are different between the
ADSP-21065L and the UART. The CPLD corrects for these differences. Additionally, there is a
minimum time restraint between subsequent access to the UART. The CPLD accounts for this
needed time delay.
3. Translates ADSP-21065L read and write cycles into cycles appropriate for the EMAFE.
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