e_rd_bar <= rd_bar;
e_wr_bar <= wr_bar;
e_cs_bar <= '0' when ((addr = "0001") AND (cs_bar = '0')) else '1';
e_addr <= '0' when ((addr = "0000") AND (cs_bar = '0')AND
(wr_bar = '0')) else '1';
-- *************************************************
-- Wait Generator for EPROM
-- *************************************************
-- Delay the accesses to the EPROM since the DSP will try to
-- access it at 30 MHz.
wait_state: process(rd_bar, bms_bar, present_wstate)-- State selection and ack
control
variable rd : std_logic;
variable bms : std_logic;
begin
rd := not rd_bar;
bms := not bms_bar;
case present_wstate is
when WAIT0 =>
if ((bms = '1') AND (RD = '1')) then -- Check for EPROM RD
w_ack <= '0'; -- Yes .. Delay
w_ack_v <= '1';
next_wstate <= WAIT1;
else -- No, ignore
w_ack <= '1';
w_ack_v <= '0';
end if;
when WAIT1 => -- Continue Delay
w_ack <= '0';
w_ack_v <= '1';
next_wstate <= WAIT2;
when WAIT2 => -- Continue Delay
w_ack <= '0';
w_ack_v <= '1';
next_wstate <= WAIT3;
when WAIT3 => -- Continue Delay
w_ack <= '0';
w_ack_v <= '1';
next_wstate <= WAIT4;
when WAIT4 => -- Continue Delay
w_ack <= '0';
w_ack_v <= '1';
next_wstate <= WAIT5;
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