A
A
B
B
C
C
D
D
E
E
4
4
3
3
2
2
1
1
65-000299- 02 (1125-01-001-0201)
2.0
ADSP-21065L EZ- LAB
Ana log Devices, Inc.
One Tech nology Way.
B
4
8
Wed nesday, November 18, 1998
{Page Title}
Norwood, MA 02062
Kris Stafford
{Filename}
Title
Size
Documen t Number
Rev
Date
Sheet
of
Approved
Drawn By
Filename
Designed by Paragon Innovations, Inc .
email: info@paragon -tx.com
DSP
Proc. Main
IRQ0#
IRQ1#
IRQ2#
HBG#
CS#
REDY#
DSP_CLK
PWM_EVENT0
PWM_EVENT1
MS2#
MS3#
RD#
WR#
SW#
ACK
BR1#
BR2#
HBR#
RXCLK0
TXCLK0
TFS0
RFS0
DT0A
DT0B
DR0A
DR0B
RXCLK1
RFS1
DR1A
DR1B
TXCLK1
TFS1
DT1A
DT1B
DQM
SDWE#
CAS#
RAS#
SDA10
SDCKE
SDCLK0
DMAR1#
DMAR2#
DMAG1#
DMAG2#
FLAG[4..9]
FLAG[0..3]
MFLAG
RESET#
CPA#
SBTS#
D[0..31]
A[0..23]
PROM_CS#
MS0#
MS1#
CODEC_ON#
Mem
Memory
D[0..31]
A[0..19]
PROM_CS#
RD#
SDA10
MS3#
RAS#
CAS#
SDWE#
DQM
SDCKE
SDCLK0
Codec
Codec
DT1A
RFS1
DR1A
RXCLK1
TXCLK1
CODEC_CS0
CODEC_CS1
CHAIN_IN
CHAIN_CLK
CODEC_ON#
CODEC_RST#
I/O
I/O
SBTS#
CPA#
MS1#
RD#
CS#
DMAR1#
BR1#
MS2#
ACK
HBG#
MS0#
SW#
WR#
MS3#
HBR#
BR2#
DMAG1#
RESET#
REDY#
PWM_EVENT0
PWM_EVENT1
DMAG2#
EXT_CLK
A[0..23]
IRQ2#
IRQ1#
DMAR2#
IRQ0#
D[0..31]
FLAG[0..3]
FLAG[4..9]
EMAFE
EMAFE
MFLAG
TFS1
RFS1
DT1A
DT1B
DR1A
DR1B
RXCLK1
TXCLK1
TFS0
DR0A
RFS0
TXCLK0
DT0A
DT0B
RXCLK0
DR0B
EMAFE_WR#
EMAFE_RD#
EMAFE_CS#
CODEC_CS0
CODEC_CS1
CHAIN_IN
CHAIN_CLK
EMAFE_ADDR
D[0..15]
IRQ1#
UART-CPLD
UART-CPLD
RST
PLD_CLK
EMAFE_WR#
EMAFE_RD#
EMAFE_CS#
EMAFE_ADDR
PROM_CS*
A[0..5]
D[0..7]
ACK
WR#
MS1#
RD#
IRQ0#
CODEC_RST#
PWR/RST
PWR/RST
DSP_CLK
PLD_CLK
EXT_CLK
RESET#
RST
A[0..23]
D[0..31]
FLAG[0..3]
FLAG[4..9]
PLD_CLK
RST
PLD_CLK
RST
www.BDTIC.com/ADI
