bms_bar : in std_logic; -- Wait (EPROM) input
u_en_bar, u_rd_bar, u_wr_bar : out std_logic; -- UART Outputs
ack : out std_logic; -- to DSP
e_cs_bar, e_rd_bar, e_wr_bar,
e_addr : out std_logic; -- EMAFE Outputs
codec_rst_bar : out std_logic); -- CODEC Reset
attribute pin_avoid of interface:entity is "1 13 21 33";
-- avoiding programming contol pins
-- Need to lock pin numbers, to prevent accidental changes
attribute pin_numbers of interface:entity is
"reset:26 clk:7 wr_bar:29 rd_bar:9 cs_bar:15 "
& "addr(3):11 addr(2):12 addr(1):14 addr(0):27 "
& "bms_bar:10 u_en_bar:30 u_rd_bar:32 u_wr_bar:22 "
& "ack:18 e_cs_bar:36 e_rd_bar:23 e_wr_bar:24 e_addr:37 "
& "codec_rst_bar:8 ";
end interface;
architecture state_machine of interface is
type StateType is (IDLE, CS1, CS2, WR1, WR2, WR3, WR4, WR_D1, ENDW1,
ENDW2, ENDW3, ENDW4, CS3, CS4, CS5, CS6, RD1,
RD2, RD3, RD4, ENDR1);
signal present_state, next_state : StateType;
signal u_ack : std_logic;
-- ACK signal generated from UART
signal u_ack_v : std_logic;
-- UART ACK valid signal
signal w_ack : std_logic;
-- ACK signal generated from EPROM
signal w_ack_v : std_logic;
-- EPROM ACK valid signal
signal uart_ctrl_d: std_logic_vector(2 downto 0);
-- (u_rd_bar_d,
-- u_en_bar_d, u_wr_bar_d)
-- next state of uart
-- control signals
type WAIT_STATE is (WAIT0, WAIT1, WAIT2, WAIT3, WAIT4, WAIT5,
WAIT6);
signal present_wstate, next_wstate : WAIT_STATE;
begin
-- *************************************************
-- UART Control logic
-- *************************************************
uart_state:process(present_state, cs_bar, rd_bar, wr_bar, addr)
variable rd : std_logic;
variable wr : std_logic;
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