AD1849K
REV. 0
–23–
No external circuitry is required for driving a single speaker
from the AD1849K’s mono outputs as shown in Figure 16.
Note that this output is differential. Analog Devices guarantees
specified distortion performance for speaker impedances of 48
Ω
or greater. Lower impedance speakers can be used, but at the
cost of some distortion. When driving speakers much less than
48
Ω
, a power amp should be used. The AD1849K can drive
speakers of 32
Ω
or greater.
MOUT
MOUTR
Z
≥
32
Ω
Figure 16. AD1849K External Mono Speaker Connector
Figure 17 illustrates reference bypassing. V
REF
should only be
connected to its bypass capacitors, which should be located as
close to Pin 21 as possible (especially the 0.1
µ
F capacitor).
10
µ
F
10
µ
F
CMOUT
0.1
µ
F
V
REF
Figure 17. AD1849K Voltage Reference Bypassing
Figure 18 illustrates signal-path filtering capacitors, C0 and C1.
The AD1849K must use 1.0
µ
F capacitors.
C1
C0
1
µ
F
1
µ
F
Figure 18. AD1849K External Filter Capacitor Connections
The crystals shown in the crystal connection circuitry of Figure 19
should be fundamental-mode and parallel-tuned. Two sources for
the exact crystals specified are Component Marketing Services
in Massachusetts, U.S. at 617-762-4339 and Cardinal Compo-
nents in New Jersey, U.S. at 201-746-0333. Note that using the
exact data sheet frequencies is not required and that external
clock sources can be used to overdrive the AD1849K’s internal
oscillators. (See the description of the MCK1:0 control bits
above.) If using an external clock source, apply it to the crystal
input pins while leaving the crystal output pins unconnected.
Attention should be paid to providing low jitter external input
clocks.
COUT1
CIN1
20–64pF
24.576MHz
20–64pF
COUT2
CIN2
20–64pF
16.9344MHz
20–64pF
Figure 19. AD1849K Crystal Connections
Good, standard engineering practices should be applied for
power-supply decoupling. Decoupling capacitors should be
placed as close as possible to package pins. If a separate analog
power supply is not available, we recommend the circuit shown
in Figure 20 for using a 5 V supply. Ferrite beads suffice
for the inductors shown. This circuitry should be as close to the
supply pins as is practical.
+5V SUPPLY
1.6
Ω
1
µ
F
0.1
µ
F
V
DD
0.1
µ
F
FERRITE
0.1
µ
F
0.1
µ
F
0.1
µ
F
FERRITE
0.1
µ
F
1
µ
F
1
µ
F
V
DD
V
DD
V
CC
V
CC
Figure 20. AD1849K Recommended Power Supply
Bypassing
The two PIO pins must be pulled HI, as they have open drain
outputs. Analog Devices also recommends pull-down resistors
for SCLK, FSYNC, SDTX, SDRX, and TSIN to provide
margin against system noise. CLKIN, CIN1, and CIN2, if not
used, should be grounded. A typical connection diagram is
shown in Figure 21, which serves to summarize the preceding
application circuits.
