AD1849K
REV. 0
–20–
RESET
should be asserted when power is first applied to the
AD1849K.
RESET
should be asserted for a minimum of 50 ms
at power-up or when leaving the power-down mode to allow the
power supplies and the voltage reference to settle. Any time
RESET
is asserted during normal operation, it should remain
asserted for a minimum of 100 ns to insure a complete reset.
Note that an autocalibration sequence will always occur when
RESET
is deasserted, in addition to on the Control Mode to
Data Mode transition.
Coming out of either reset or power down, the state of the Data/
Control pin (D/
C
) will determine whether the Codec is in Data
Mode or Control Mode. In the unlikely event that the control
register defaults are desired for Codec operation, it is possible to
go directly from reset or power down to Data Mode and begin
audio operation.
Control Mode
More typically, users coming out of reset or power down will
want to change the control register defaults by transmitting a
Control Word in Control Mode. The user of the AD1849K
SoundPort Codec can also enter Control Mode at any time
during normal Data Mode operation. The D/
C
pin is provided
to make this possible. The Codec enters Control Mode when
the D/
C
pin is driven LO or held LO when coming out of reset
and/or power down.
In Control Mode, the location of a word within a frame is
determined solely by the behavior of the TSIN and TSOUT
signals. Each Codec by itself does not care where the frame
boundaries fall as defined by the system. The contents of the
frame size select (FSEL1:0, Control Word Bits 43 and 42) bits
are irrelevant to the operation of each AD1849K in Control
Mode. In Control Mode, a Codec requires 64 SCLK cycles to
be fully programmed. Additional SCLK cycles (more than 64)
that occur before the end of the frame will be ignored.
If four Codecs, for example, were daisy-chained, then each
Codec would receive TSIN every 256 bits. In this case, Codec
#2’s input Control Word will be positioned between Bit 64 and
Bit 127 in the input frame.
Control Word Echo
While in Control Mode, the AD1849K Codec will echo the
Control Word received as a serial input on the SDRX pin as a
serial output in the next frame on the SDTX pin. (SDTX will
be enabled regardless of the setting of the TXDIS bit, Control
Word Bit 40.) This echoing of the control information allows
the external controller to confirm that the Codec has received
the intended Control Word. For the four Codec daisy chain
example above, the Control Word will be echoed bit for bit as
an output between Bit 64 and Bit 127 in the next output frame.
In general, in Control Mode, the location of the echo Control
Word within a frame will be at the same word location as the
input Control Word.
In the first frame of Control Mode, the AD1849K will output a
Control Word that reflects the control register values operative
during the most recent Data Mode operation. If Control Mode
was entered prior to any Data Mode operation, this first output
word will simply reflect the standard default settings. DCB will
always be “1” in the first output echoed Control Word.
DCB Handshaking Protocol
The D/
C
pin can make transitions completely asynchronously to
internal Codec operation. This fact necessitates a handshaking
protocol to ensure a smooth transition between serial bus
masters (i.e., the external controller and the Codec) and
guarantee unambiguous serial bus ownership. This software
handshake protocol for Control Mode to Data Mode transitions
makes use of the Data/Control Bit (DCB) in the Control Mode
Control Word (Bit 58). Prior to initiating the change to Control
Mode, the external controller should gradually attenuate the
audio outputs. The DCB handshake protocol requires the
following steps:
Enter Control Mode
The external controller drives the D/
C
pin LO, forcing the
Codec into Control Mode as a slave. The DCB transmitted
from the external controller to the Codec may be “0” or “1” at
this point in the handshake.
When ITS = 0 (Control Word Bit 47) and the Codec was oper-
ating as the master in the preceding Data Mode, immediately
after D/
C
goes LO, the Codec will drive FSYNC and TSOUT
LO for one SCLK period, then three-state FSYNC. SDTX is
three-stated immediately after D/
C
goes LO. TSOUT is not
three-stated. The Codec will drive SCLK for three (3) SCLK
periods after D/
C
goes LO and then three-state SCLK. The
external controller must wait at least three (3) SCLK periods
after it drives D/
C
LO, and then start driving SCLK.
When ITS = 1 (Control Word Bit 47) and the Codec was
operating as the master in the preceding Data Mode, the Codec
will three-state FSYNC, SDTX, and SCLK immediately after
D/
C
goes LO. TSOUT is driven LO immediately after D/
C
goes LO and is not three-stated. The external controller may
start driving SCLK immediately.
When ITS = 0 and the external controller was operating as the
master in the preceding Data Mode, the external controller
must continue to supply SCLK to the slave Codec for at least
three (3) SCLK periods after D/
C
goes LO before a Control
Mode TSIN is issued to the Codec. TSIN must be held LO
externally until the first Control Word in Control Mode is
supplied by the external controller. This prevents false starts
and can be easily accomplished by using a pull-down resistor on
TSIN as recommended. The slave Codec drives TSOUT and
SDTX LO, then three-states SDTX, all within 1 1/2 (one and
one half) SCLK periods after D/
C
goes LO. TSOUT is not
three-stated.
When ITS = 1 and the external controller was operating as the
master in the preceding Data Mode, the external controller
must continue to supply SCLK to the slave Codec. A Control
Mode TSIN should be issued to the Codec three or more
SCLK periods after D/
C
goes LO. The slave Codec drives
TSOUT LO and three-states SDTX immediately after D/
C
goes LO. TSOUT is not three-stated.
The Codec initializes its Data Mode Control Registers to the
defaults identified above, which among other actions, mutes all
audio outputs.
First DCB Interlock
When the external controller is ready to continue with the DCB
handshake, the Control Word sent by the external controller
should have the DCB reset to “0” along with arbitrary control
information (i.e., the control information does not have to be
valid, although if it is valid, it allows the external controller to
verify that the echoed Control Word is correct). The external
controller should continue to transmit this bit pattern with
