AD1849K
REV. 0
–17–
SERIAL INTERFACE
A single serial interface on the AD1849K provides for the trans-
fer of both data and control information. This interface is simi-
lar to AT&T’s Concentrated Highway Interface (CHI), allowing
simple connection with ISDN and other telecommunication
devices. The AD1849K’s implementation also allows a no-glue
direct connection to members of Analog Devices’ family of
fixed-point DSP processors, including the ADSP-2101, the
ADSP-2105, the ADSP-2111, and the ADSP-2115.
Frames and Words
The AD1849K serial interface supports time-division multi-
plexing. Up to four AD1849K Codecs or compatible devices
can be daisy-chained on the same serial lines. A “frame” can
consist of one, two, or four 64-bit “words.” Thus, frames can be
64, 128, or 256 bits in length as specified by the FSEL bits in
Control Byte 3. Only 64 bits of each frame, a “word,” contain
meaningful data and/or control information for a particular
Codec. See Figure 4 below.
ONE WORD/FRAME WORD #1
0 63
TWO WORDS/FRAME WORD #1 WORD #2
0 63 64 127
FOUR WORDS/FRAME WORD #1 WORD #2 WORD #3 WORD #4
0 63 64 127 128 191 192 255
Figure 4. Frames and Words
The AD1849K supports two types of words: Data Words and
Control Words. The proper interpretation of a word is deter-
mined by the state of the asynchronous Data/Control (D/
C
) pin.
The D/
C
pin establishes whether the SoundPort Codec is in the
“Data” mode or “Control” mode. Transitions between these
modes require an adherence to a handshaking protocol to pre-
vent ambiguous bus ownership. The Data/ Control transition
protocol is described below in a separate section.
Clocks and the Serial Interface
The primary pins of the AD1849K’s serial interface are the
serial data receive (SDRX) input pin. The serial data transmit
(SRTX) pin, the serial data bit clock (SCLK) pin, the frame
sync output (FSYNC) pin, the chaining word input (TSIN) pin,
and the chaining word output (TSOUT) pin. The AD1849K
can operate in either master mode—in which case SCLK and
FSYNC are outputs and TSIN is an input—or in slave mode—
in which case SCLK and TSIN are inputs and FSYNC is three-
stated. If the AD1849K is in master mode, the internally
selected clock source is used to drive SCLK and FSYNC. Note
that in Control Mode, the Codec always behaves as a slave,
regardless of the current state of the MS (Master/Slave) bit.
The five possible combinations of clock source and master/slave
are summarized in Figure 5.
INTERNAL OSCILLATORS
YES
CONDITIONAL
CLKIN
YES
CONDITIONAL
SCLK
IMPOSSIBLE
YES
MASTER
SLAVE
Figure 5. Clock Source and Master/Slave Combinations
Recommended modes are indicated above by “yes.” Note that
Codec performance is improved with a clean clock source, and
in many systems the lowest jitter clocks available will be those
generated by the Codec’s internal oscillators. Conversely, SCLK
in many systems will be the noisiest source. The master/SCLK
clock source combination is impossible because selecting SCLK
as the clock source overrides the MS control bit, forcing slave
mode. (The SCLK pin cannot be driving out if it is simulta-
neously receiving an external clock.)
The internal oscillators or CLKIN can be the clock source when
the serial interface is in slave mode provided that all clocks
applied to the AD1849K SoundPort Codec are derived from the
same external source. Precise phase alignment of the clocks is
not necessary, rather the requirement is that there is no
frequency drift between the clocks.
In master mode, the SCLK output frequency is determined by
the number of bits per frame selected (FSEL) and the sampling
frequency, F
S
. In short, SCLK = FSEL
×
F
S
in master mode.
Timing Relationships
Input data (except PIO) is clocked by the falling edge of SCLK.
Data outputs (except PIO) begin driving on the rising edge of
SCLK and are always valid well before the falling edge of
SCLK.
Word chaining input, TSIN, indicates to a particular Codec the
beginning of its word within a frame in both slave and master
modes. The master mode Codec will generate a FSYNC output
which indicates the beginning of a frame. In single Codec
systems, the master’s FSYNC output should be tied to the
master’s TSIN input to indicate that the beginning of the frame
is also the beginning of its word. In multiple Codec daisy-chain
systems, the master’s FSYNC output should be tied to the
TSIN input of the Coded (either the master or one of the
slaves) which is intended to receive the first word in the frame.
FSYNC and TSIN are completely independent, and nothing
about the wiring of FSYNC to TSIN is determined by master or
slave status (i.e., the master can own any one of the words in the
frame). The master Codec’s FSYNC can also be tied to all of
the slave Codecs’ FSYNC pins. When a slave, a Codec’s
FSYNC output is three-stated. Thus, it can be connected to a
master’s FSYNC without consequence. See “Daisy-Chaining
Multiple Codecs” below for more details.
The FSYNC rate is always equal to the data conversion
sampling frequency, F
S
. In Data Mode, the key significance of
“frames” are to synchronize the transfer of digital data between
an AD1849K’s internal ADCs and DACs and its serial interface
circuitry. If, for example, a Codec has been programmed for two
words per frame (FSEL = “1”), then it will trigger the data
converters and transfer data between the converters and the
interface every 128 SCLKs. The TSIN input signals the Codec
where its word begins within the frame. In Control Mode, frame
size is irrelevant to the operation of any particular Codec; TSIN
and TSOUT are sufficient to convey all the information
required.
