AD1849K
REV. 0
–16–
Control Register Defaults
Upon coming out of
RESET
or Power Down, internal control registers will be initialized to the following values:
Defaults Calming Out of
RESET
or Power Down
MB
0
Mic Input Applied to +20 dB Fixed Gain Block
OLB
0
Full-Scale Line 0 Output 2.8 V p-p, Full-Scale Line 1 Output 4.0 V p-p, Full-Scale Mono Speaker
Output 8.0 V p-p
DCB
1
Data/Control Bit HI
AC
0
Autocalibration Disabled
DFR2:0
0
8 or 5.5125 kHz
ST
0
Monophonic Mode
DF1:0
1
8-Bit
µ
-Law Data
ITS
0
FSYNC, SDTX and SCLK Three-State within 3 SCLK Cycles after D/
C
Goes LO
MCK2:0
0
Serial Bit Clock [SCLK] is the Master Clock
FSEL1:0
2
256 Bits per Frame
MS
0
Slave Mode
TXDIS
1
Three-State Serial Data Output
ENL
0
Loopback Disabled
ADL
0
Digital Loopback
PIO1:0
3
“1”s, i.e., Three-State for the Open Collector Outputs
OM1:0
0
Mute Line 0 and Line 1 Outputs
LO5:0
63
Mute Left DAC
ADI
1
ADC Data Invalid, Autocalibration in Progress
SM
0
Mute Mono Speaker
RO5:0
63
Mute Right DAC
OVR
0
No Overrange
IS
0
Line-Level Stereo Inputs
LG3:0
0
No Gain on Left Channel
MA3:0
15
No Mix
RG3:0
0
No Gain on Right Channel
Also, when making a transition from Control Mode to Data Mode, those control register values that are not changeable in Control
Mode get reset to the defaults above (except PIO). The control registers that can be changed in Control Mode will have the values
they were just assigned. The subset of the above list of control registers that are assigned default values on the transition from
Control Mode to Data Mode are:
Defaults at a Control-to-Data Mode Transition
OM1:0
0
Mute Line 0 and Line 1
LO5:0
63
Mute Left DAC
SM
0
Mute Mono Speaker
RO5:0
63
Mute Right DAC
OVR
0
No Overrange
IS
0
Line-Level Stereo Inputs
LG3:0
0
No Gain
MA3:0
15
No Mix
RG3:0
0
No Gain
Note that all these defaults can be changed with control information in the first Data Word. Note also that the PIO bits in the output
serial streams always reflect the values most recently read from the external PIO pins. (See “Parallel I/O Bits” below for timing
details.) A Control-to-Data Mode transition is no exception.
An important consequence of these defaults is that the AD1849K Codec always comes out of reset or power down in slave mode with an
externally supplied serial bit clock (SCLK) as the clock source. An external device must supply the serial bit clock and the chaining word
input signal (TSIN) initially. (See “Codec Startup, Modes, and Transitions” below for more details.)
