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AD1849K

REV. 0

–6–

ABSOLUTE MAXIMUM RATINGS*

Min

Max

Units

Power Supplies

Digital (V

DD

)

–0.3

 6.0

V

Analog (V

CC

)

–0.3

 6.0

V

Input Current

(Except Supply Pins and MOUT,

±

10.0

mA

MOUTR, LOUT1R, LOUT1L,
LOUT1C)

Analog Input Voltage (Signal Pins)

–0.3

(V

CC

+) + 0.3

V

Digital Input Voltage (Signal Pins)

–0.3

(V

DD

+) + 0.3

V

Ambient Temperature (Operating)

0

+70

°

C

Storage Temperature

–65

+150

°

C

ESD Tolerance (Human Body

500

V

Model per Method 3015.2

of MIL-STD-883B)

WARNING: CMOS device. May be susceptible to high voltage
transient-induced latchup.

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature

Package

Package

Model

Range

Description

Option

AD1849KP

0

°

C to +70

°

C

44-Lead PLCC

P-44A

WARNING!

ESD SENSITIVE DEVICE

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1849K features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

44-Lead Plastic Leaded Chip Carrier Pinout

0.656 (16.66)

0.650 (16.51)

SQ

0.695 (17.65)

0.685 (17.40)

SQ

0.048 (1.21)

0.042 (1.07)

0.048 (1.21)

0.042 (1.07)

40

 6

TOP VIEW

39

29

18

17

PIN 1

IDENTIFIER

7

28

0.032 (0.81)

0.026 (0.66)

0.021 (0.53)

0.013 (0.33)

0.056 (1.42)

0.042 (1.07)

0.025 (0.63)

0.015 (0.38)

0.180 (4.57)

0.165 (4.19)

0.63 (16.00)

0.59 (14.99)

0.110 (2.79)

0.085 (2.16)

0.040 (1.01)

0.025 (0.64)

0.050
(1.27)
BSC

0.020 (0.50) R

PIN 1

IDENTIFIER

BOTTOM VIEW

44-Lead TQFP

AD1849KST

 

SoundPort®

STEREO CODEC

23

24

25

26

27

28

29

30

31

32

33

V

DD

PIO0

N/C

LOUT0R

LOUT0L

LOUT1L

LOUT1C

PIO1

LOUT1R

GNDD

1

2

3

4

5

6

7

8

9

10

11

COUT1

GNDD

COUT2

PDN

C0

MINR

LINR

MINL

CIN2

V

DD

36

35

34

44

43

42

41

40

39

38

37

CIN1

CLKIN

V

DD

GNDD

SDRX

SDTX

SCLK

FSYNC

CLKOUT

TSOUT

TSIN

12

13

14

15

16

17

18

19

20

21

22

LINL

C1

V

REF

GNDA

CMOUT

V

CC

GNDA

N/C

MOUT

MOUTR

V

CC

N/C = NO CONNECT

RESET

D/C

Summary of Contents for AD1849K

Page 1: ...are available over a single bidirectional serial interface that also sup ports 16 bit digital input to the DACs and control information The AD1849K can accept and generate 8 bit law or A law compande...

Page 2: ...Line 1 External Load Capacitance 100 pF Line 0 1 ANALOG INPUT Min Typ Max Units Input Voltage RMS Values Assume Sine Wave Input Line and Mic with 0 dB Gain 0 94 0 99 1 04 V rms 2 66 2 80 2 94 V p p Mi...

Page 3: ...Interchannel Gain Mismatch Line and Mic 0 3 dB Difference of Gain Errors DIGITAL TO ANALOG CONVERTERS Min Typ Max Units Resolution 16 Bits DAC Dynamic Range 60 dB Input THD N Referenced 80 86 dB to Fu...

Page 4: ...Scale Output Voltage Line 0 1 0 707 V rms OLB 1 1 85 2 0 2 1 V p p Full Scale Output Voltage Line 0 1 0 V rms OLB 0 2 8 V p p Full Scale Output Voltage Line 1 4 0 V p p OLB 0 Full Scale Output Voltage...

Page 5: ...o Valid tZV 15 ns Output Valid to Hi Z tVZ 20 ns Power Up RESET LO Time 50 ms Operating RESET LO Time 100 ns POWER SUPPLY Min Typ Max Units Power Supply Voltage Range 4 75 5 25 V Digital and Analog Po...

Page 6: ...atic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD1849K features propri...

Page 7: ...l Line Input MINL 17 11 I Left Channel Microphone Input 20 dB from Line Level if MB 0 or Line Level if MB 1 MINR 15 9 I Right Channel Microphone Input 20 dB from Line Level if MB 0 or Line Level if MB...

Page 8: ...riod is 10 7 milliseconds at a 48 kHz sampling rate and 64 milliseconds at an 8 kHz sampling rate Time out ms 512 Sampling Rate kHz Monitor Mix A monitor mix is supported that digitally mixes a portio...

Page 9: ...d to prevent undesired outputs Monitor mix will be automatically disabled by the Codec During the autocalibration sequence the serial data output from the ADCs is meaningless and the ADI bit is assert...

Page 10: ...provided to generate a wide range of sample rates The oscillators for these crystals are on the AD1849K as is a multiplexer for selecting between them They can be overdriven with external clocks by th...

Page 11: ...ntrol Byte 1 Status Register Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 0 0 1 MB OLB DCB 0 AC 63 62 61 60 59 58 57 56 MB Mic bypass 0 Mic inputs applied to 20 dB fixed gain block 1 Mic in...

Page 12: ...4 43 42 41 40 ITS Immediate three state 0 FSYNC SDTX and SCLK three state within 3 SCLK cycles after D C goes LO 1 FSYNC SDTX and SCLK three state immediately after D C goes LO MCK2 0 Clock source sel...

Page 13: ...PIO1 0 Parallel I O bits for system signaling PIO bits do not affect Codec operation Control Byte 6 Reserved Register Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 0 0 0 0 0 0 0 0 23 22 21...

Page 14: ...4 R13 R12 R11 R10 R9 R8 47 46 45 44 43 42 41 40 In 16 bit linear PCM mode this byte contains the upper eight bits of the right audio data sample In the 8 bit companded and linear modes this byte conta...

Page 15: ...ther ADC channel is driven beyond the specified input range It is sticky i e it remains set until explicitly cleared by writing a 0 to OVR A 1 written to OVR is ignored allowing OVR to remain 0 until...

Page 16: ...transition from Control Mode to Data Mode those control register values that are not changeable in Control Mode get reset to the defaults above except PIO The control registers that can be changed in...

Page 17: ...e and in many systems the lowest jitter clocks available will be those generated by the Codec s internal oscillators Conversely SCLK in many systems will be the noisiest source The master SCLK clock s...

Page 18: ...e host for operation Subsequent transitions to Control Mode after initialization are expected to be relatively infrequent Control information that is likely to change frequently e g gain levels is tra...

Page 19: ...provides a convenient mechanism for transferring signaling information between the serial data and control streams and the external pair of bidirectional pins also named PIO1 and PIO0 The states of th...

Page 20: ...Handshaking Protocol The D C pin can make transitions completely asynchronously to internal Codec operation This fact necessitates a handshaking protocol to ensure a smooth transition between serial...

Page 21: ...andshake the AD1849K and the CS4215 DCB protocols are equivalent Control Mode to Data Mode Transition and Autocalibration The AD1849K will enter Data Mode when the asynchronous D C signal goes HI The...

Page 22: ...OR AD820 0 33 F 0 33 F Figure 12 AD1849K Phantom Powered Microphone Input Circuit Figure 13 shows ac coupled line outputs The resistors are used to center the output signals around analog ground If d...

Page 23: ...201 746 0333 Note that using the exact data sheet frequencies is not required and that external clock sources can be used to overdrive the AD1849K s internal oscillators See the description of the MCK...

Page 24: ...ort Codec to four of Analog Devices Fixed Point DS Ps The ADSP 2111 ADSP 2101 and ADSP 2115 use their multichannel serial port for the data interface and flag outputs for D C The ADSP 2105 has a singl...

Page 25: ...single pole active filter requiring a dual op amp Though overkill for the AD1849K this input circuit will work with the AD1849K as well The AD1849K was designed to require no external low pass filter...

Page 26: ...MPLE FREQUENCY FS Figure 25 AD1849K Analog to Digital Frequency Response Transition Band Full Scale Line Level Inputs 0 dB Gain 10 120 1 0 90 110 0 1 100 0 0 60 80 70 50 30 20 0 10 40 0 8 0 9 0 7 0 6...

Page 27: ...TROL REGISTERS 11 Control Mode Control Registers 11 Data Mode Data and Control Registers 14 Control Register Defaults 16 SERIAL INTERFACE 17 Frames and Words 17 Clocks and the Serial Interface 17 Timi...

Page 28: ...0 013 0 33 0 056 1 42 0 042 1 07 0 025 0 63 0 015 0 38 0 180 4 57 0 165 4 19 0 63 16 00 0 59 14 99 0 110 2 79 0 085 2 16 0 040 1 01 0 025 0 64 0 050 1 27 BSC 0 020 0 50 R PIN 1 IDENTIFIER BOTTOM VIEW...

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