When soldering, heat the PCB pad and the lead of the component, not the solder. After several seconds of the
component lead in contact with the hot soldering iron apply solder smoothly and evenly onto the PCB pad
and component lead not the soldering iron. Do not touch or move the replacement part until the solder has
cooled. Cold solder and bad solder joints can cause more problems.
Use the unit's chassis ground connection - i.e. connect to an earth ground to avoid a static discharge to a static
sensitive component. Handle all AMPTEC 601ES DMM internal components as if they are static sensitive if
you are not sure.
E-5. Circuit Descriptions
E-5.1 Model 601ES IC 401 - DVM IC - MAX7129 - Detailed Description
The MAX7129 is a uniquely designed single chip A/D converter. The AMPTEC 601ES Explosive Safety
Meter DVM measurement circuit features a new successive integration" technique to achieve 5µV resolution
on a 100mV full-scale range. To achieve this resolution a 10:1 improvement in noise performance over pre-
vious monolithic CMOS A/D converters was used. Previous integrating converters used an external capacitor
to store an offset correction voltage (dual slope integration). This technique worked well but greatly in-
creased the equivalent noise bandwidth of the converter. The MAX7129 removed this source of error (noise)
by not using an auto-zero capacitor. Offsets are cancelled using digital techniques instead. Savings in exter-
nal parts cost are realized as well as improved noise performance and elimination of a source of electromag-
netic and electrostatic pick-up.
In the overall Functional Block Diagram of the MAX7129 the heart of this A/D converter is the sequence
counter/decoder which drives the control logic and keeps track of the many separate phases required for each
conversion cycle. The sequence counter is constantly running and is a separate counter from the up/down
results counter which is activated only when the integrator is de-integrating. At the end of a conversion the
data remaining in the results counter is latched, decoded and multiplexed to the liquid crystal display.
The analog section block diagram shown in FIG. H-7 included all of the analog switches used to configure
the voltage sources and amplifiers in the different phases of the cycle. The input and reference switching
schemes are very similar to those in other less accurate integrating A/D converters. There are 5 basic config-
urations used in the full conversion cycle.
FIG. H-9 illustrates a typical waveform on the integrator output. INT, INT1, and INT2 all refer to the signal
integrate phase where the input voltage is applied to the integrator amplifier via the buffer amplifier. In this
phase, the integrator ramps over a fixed period of time in a direction opposite polarity to the input voltage to
the display driver for decoding and multiplexing
DE1, DE2 and DE3 are the de-integrate phases where the reference capacitor is switched in series with the
buffer amplifier and the integrator ramps back down the level it started from before integrating. However,
since the de-integration phase can terminate only at a clock pulse transition, there is always a small overshoot
of the integrator past the starting point. The ICL7129 amplifies this overshoot by 10 and DE2 begins.
Similarly DE2's overshoot is amplified by 10 and DE3 begins. At the end of DE3 the results counter holds a
number with 5½ digits of resolution. This was obtained by feeding counts into the results counter at the 3½
digit level during DE1, into the 4½ digit level during DE2 and the 5½ digit level for De3. The effects of off-
set in the buffer, integrator, and comparator can now be cancelled by repeating this entire sequence with the
inputs shorted and subtracting the results from the original reading. For this phase INT2 switch is closed to
give the same common-mode voltage as the measurement cycle. This assures excellent CMRR. At the end
Of the cycle the data in the up/down results counter is accurate to 0.02% of full scale and is sen.
Sect. E - General Operation and Design
17
