○
CB processing with HARQ buffer management in lookaside mode
Note: The Zynq Ult RFSoC ZU48DR device also supports concurrent 4G LTE/5G NR L1 offload,
assuming that the necessary hardware resources are available.
The T2 card value proposition is in offloading CPU intensive encode and decode computations
involving LDPC operations, thereby reducing costly CPU resources. The Zynq Ult RFSoC
has hard IP blocks for SD-FEC (eight SD-FEC cores per device) which can be configured to run
LDPC encode and decode operations.
Hardware Overview
The following high-level block diagram of the T2 card provides an overview of the hardware
features.
Figure 2: T2 Card High-Level Block Diagram
Zynq Ult RFSoC
SC MSP432
Power
Supply
Unit
NOR
Flash
PL DDR
Controller
(Bank 67,
68, 69)
PS MIO
(Bank
500)
PL GTY PCIe 4
(Bank 128, 129, 130, 131)
HHHL Single Slot
PCIe Gen3 x16 /
PCIe Gen4 x8 Bifurcated
XCZU48DR- 2FSVG1517E
PS DDR
Controller
(Bank 504)
Deb
ug Connector
1GB
DDR4
x16
1GB
DDR4
x16
1GB
DDR4
x16
ECC x8
1GB
DDR4
x16
X8
1GB
DDR4
x16
1GB
DDR4
x16
ECC x8
OSC
50 MHz
OSC
300 MHz
12V
3.3V
8x SD-FEC
(LDPC/Turbo)
X25345-051221
The T2 card hardware features are as follows:
• Zynq Ult RFSoC device targeting L1 channel coding
• NOR flash (2x 256 MB in dual QSPI mode) for ZU48DR Zynq Ult RFSoC image
storage
Chapter 1: Introduction
UG1496 (v1.0) June 15, 2022
T2 Telco Accelerator Card User Guide
4
