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Table 2: DDR4 PL Interface Pin Map (cont'd)

Pin Number

Signal Name

Description

I/O

A16

PL_DDR4_1_DQ46

DDR4 Data I/O 46

Bidirectional

A17

PL_DDR4_1_DQ47

DDR4 Data I/O 47

Bidirectional

L24

PL_DDR4_1_DQ48

DDR4 Data I/O 48

Bidirectional

H23

PL_DDR4_1_DQ49

DDR4 Data I/O 49

Bidirectional

J21

PL_DDR4_1_DQ50

DDR4 Data I/O 50

Bidirectional

H22

PL_DDR4_1_DQ51

DDR4 Data I/O 51

Bidirectional

K24

PL_DDR4_1_DQ52

DDR4 Data I/O 52

Bidirectional

G23

PL_DDR4_1_DQ53

DDR4 Data I/O 53

Bidirectional

G22

PL_DDR4_1_DQ54

DDR4 Data I/O 54

Bidirectional

H21

PL_DDR4_1_DQ55

DDR4 Data I/O 55

Bidirectional

L21

PL_DDR4_1_DQ56

DDR4 Data I/O 56

Bidirectional

L20

PL_DDR4_1_DQ57

DDR4 Data I/O 57

Bidirectional

M20

PL_DDR4_1_DQ58

DDR4 Data I/O 58

Bidirectional

M19

PL_DDR4_1_DQ59

DDR4 Data I/O 59

Bidirectional

N19

PL_DDR4_1_DQ60

DDR4 Data I/O 60

Bidirectional

L19

PL_DDR4_1_DQ61

DDR4 Data I/O 61

Bidirectional

L22

PL_DDR4_1_DQ62

DDR4 Data I/O 62

Bidirectional

L23

PL_DDR4_1_DQ63

DDR4 Data I/O 63

Bidirectional

E22

PL_DDR4_1_DQ64

DDR4 Data I/O 64 (ECC)

Bidirectional

G20

PL_DDR4_1_DQ65

DDR4 Data I/O 65 (ECC)

Bidirectional

E23

PL_DDR4_1_DQ66

DDR4 Data I/O 66 (ECC)

Bidirectional

E21

PL_DDR4_1_DQ67

DDR4 Data I/O 67 (ECC)

Bidirectional

F24

PL_DDR4_1_DQ68

DDR4 Data I/O 68 (ECC)

Bidirectional

F20

PL_DDR4_1_DQ69

DDR4 Data I/O 69 (ECC)

Bidirectional

E24

PL_DDR4_1_DQ70

DDR4 Data I/O 70 (ECC)

Bidirectional

D21

PL_DDR4_1_DQ71

DDR4 Data I/O 71 (ECC)

Bidirectional

C15

PL_DDR4_1_DQS0

DDR4 Data Strobe 0 (P)

Bidirectional

B15

PL_DDR4_1_DQS0#

DDR4 Data Strobe 0 (N)

Bidirectional

L15

PL_DDR4_1_DQS1

DDR4 Data Strobe 1 (P)

Bidirectional

L14

PL_DDR4_1_DQS1#

DDR4 Data Strobe 1 (N)

Bidirectional

K19

PL_DDR4_1_DQS2

DDR4 Data Strobe 2 (P)

Bidirectional

K18

PL_DDR4_1_DQS2#

DDR4 Data Strobe 2 (N)

Bidirectional

G19

PL_DDR4_1_DQS3

DDR4 Data Strobe 3 (P)

Bidirectional

F19

PL_DDR4_1_DQS3#

DDR4 Data Strobe 3 (N)

Bidirectional

B22

PL_DDR4_1_DQS4

DDR4 Data Strobe 4 (P)

Bidirectional

A22

PL_DDR4_1_DQS4#

DDR4 Data Strobe 4 (N)

Bidirectional

B18

PL_DDR4_1_DQS5

DDR4 Data Strobe 5 (P)

Bidirectional

B17

PL_DDR4_1_DQS5#

DDR4 Data Strobe 5 (N)

Bidirectional

J20

PL_DDR4_1_DQS6

DDR4 Data Strobe 6 (P)

Bidirectional

Chapter 3: Pin Mapping

UG1496 (v1.0) June 15, 2022

www.xilinx.com

T2 Telco Accelerator Card User Guide

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Summary of Contents for XILINX T2 Telco

Page 1: ...language from our products and related collateral We ve launched an internal initiative to remove language that could exclude people or reinforce historical biases including terms embedded in our soft...

Page 2: ...22 Chapter 6 Xilinx Design Constraints XDC File 23 Appendix A Regulatory Compliance Statements 24 FCC Class A Products 24 Safety 24 EMC Compliance 25 FCC Class A User Information 25 VCCI Class A Stat...

Page 3: ...C ZU48DR device supporting the following targeted applications 5G NR physical layer functional offload including but not limited to Low density parity check LDPC encoding and decoding Rate matching an...

Page 4: ...an overview of the hardware features Figure 2 T2 Card High Level Block Diagram Zynq UltraScale RFSoC SC MSP432 Power Supply Unit NOR Flash PL DDR Controller Bank 67 68 69 PS MIO Bank 500 PL GTY PCIe 4...

Page 5: ...er with the provided host software installation supports the following functions PCIe Gen3 x16 interface User flash image update SC firmware update DDR4 PL BERT performance and diagnostics test DDR4 P...

Page 6: ...Figure 3 Zynq UltraScale RFSoC XCZU48DR Device Chapter 1 Introduction UG1496 v1 0 June 15 2022 www xilinx com T2 Telco Accelerator Card User Guide 6 Send Feedback...

Page 7: ...n between server BMC and T2 SC and implements a thermal closed loop control mechanism for card cooling All required telemetry data including board temperatures and power consumption is available In ba...

Page 8: ...rovided through the maintenance port See Chapter 4 Maintenance Port for details LED A green power on LED is present on the I O bracket to indicate the card is powered and in operation Chapter 2 Featur...

Page 9: ...on requires x8 bifurcation to be enabled whereas Gen 3 x16 requires x16 mode PCIe Interface Pins The following table summarizes the ZU48DR PCIe interface pin map Table 1 PCIe Interface Pin Map Pin Num...

Page 10: ...P PCIe RX Data 10 P I F37 PCIE_RX11_N PCIe RX Data 11 N I F36 PCIE_RX11_P PCIe RX Data 11 P I E39 PCIE_RX12_N PCIe RX Data 12 N I E38 PCIE_RX12_P PCIe RX Data 12 P I D37 PCIE_RX13_N PCIe RX Data 13 N...

Page 11: ...CIe TX Data 12 P O C34 PCIE_TX13_N PCIe TX Data 13 N O C33 PCIE_TX13_P PCIe TX Data 13 P O B32 PCIE_TX14_N PCIe TX Data 14 N O B31 PCIE_TX14_P PCIe TX Data 14 P O A34 PCIE_TX15_N PCIe TX Data 15 N O A...

Page 12: ...dress 13 O E14 PL_DDR4_1_BA0 DDR4 Bank Address 0 O H13 PL_DDR4_1_BA1 DDR4 Bank Address 1 O F14 PL_DDR4_1_BG0 DDR4 Bank Group 0 O C12 PL_DDR4_1_DM0 DDR4 Data Mask 0 O N14 PL_DDR4_1_DM1 DDR4 Data Mask 1...

Page 13: ...nal F16 PL_DDR4_1_DQ25 DDR4 Data I O 25 Bidirectional G18 PL_DDR4_1_DQ26 DDR4 Data I O 26 Bidirectional E16 PL_DDR4_1_DQ27 DDR4 Data I O 27 Bidirectional H18 PL_DDR4_1_DQ28 DDR4 Data I O 28 Bidirectio...

Page 14: ...ECC Bidirectional G20 PL_DDR4_1_DQ65 DDR4 Data I O 65 ECC Bidirectional E23 PL_DDR4_1_DQ66 DDR4 Data I O 66 ECC Bidirectional E21 PL_DDR4_1_DQ67 DDR4 Data I O 67 ECC Bidirectional F24 PL_DDR4_1_DQ68...

Page 15: ...K13 PL_DDR4_1_CKE DDR4 Clock Enable O F11 PL_DDR4_1_CS DDR4 Chip Select O D14 PL_DDR4_1_WE DDR4 Write Enable O J10 PL_DDR4_1_ALERT DDR4 Alert I J14 PL_DDR4_1_RST DDR4 Reset O J13 PL_DDR4_1_TEN DDR4 T...

Page 16: ...M3 DDR4 Data Mask 3 O AR38 PS_DDR4_1_DM4 DDR4 Data Mask 4 O AV22 PS_DDR4_1_DQ0 DDR4 Data I O 0 Bidirectional AW24 PS_DDR4_1_DQ1 DDR4 Data I O 1 Bidirectional AW23 PS_DDR4_1_DQ2 DDR4 Data I O 2 Bidirec...

Page 17: ...Bidirectional AP36 PS_DDR4_1_DQ35 DDR4 Data I O 35 ECC Bidirectional AT39 PS_DDR4_1_DQ36 DDR4 Data I O 36 ECC Bidirectional AP35 PS_DDR4_1_DQ37 DDR4 Data I O 37 ECC Bidirectional AR36 PS_DDR4_1_DQ38...

Page 18: ...The dual QSPI mode flash has been implemented with two 2 Gb SPI NOR flash devices Micron MT25QU02GCBB8E12 0AAT The MT25QU02GCBB8E12 0AAT NOR flash devices are automotive grade for thermal design reaso...

Page 19: ...is asserted by the Zynq UltraScale RFSoC to acknowledge the power reduction request by the SC and to avoid a fatal power cutoff protection mechanism The SC is always powered UART Maintenance Port Acc...

Page 20: ...a 0 Bidirectional R27 RF_QSPI_UPR_DQ1 QSPI Upper Data 1 Bidirectional V27 RF_QSPI_UPR_DQ2 QSPI Upper Data 2 Bidirectional P28 RF_QSPI_UPR_DQ3 QSPI Upper Data 3 Bidirectional H26 PS_SOC_SCL I2C Bus to...

Page 21: ...FSoC PS applications as required JTAG to RFSoC This JTAG chain to the RFSoC can be used for communication with the Vivado Design Suite during development for programming and debug UART to SC This UART...

Page 22: ...hat this 40A maximum current limit for the combined VCCINT and SD FEC rails is observed at the maximum operating junction temperature of 100 C The card protection circuit initiates a fatal shutdown if...

Page 23: ...d card XDC file is available for download from the T Series lounge Contact your Xilinx representative for access Note There are production and prototype versions of the XDC Ensure that you have select...

Page 24: ...isted in this document IEC 62368 1 2nd Edition 2014 A11 2017 Information technology equipment Safety Part 1 General requirements EN 62368 1 2nd Edition 2014 A11 2017 Information technology equipment S...

Page 25: ...adiated and Conducted Emissions Australia New Zealand Article 58 2 of Radio Waves Act Clause 3 Korea Regulatory Compliance Markings When required these products are provided with the following product...

Page 26: ...pment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications Operation of this e...

Page 27: ...On Windows select Start All Programs Xilinx Design Tools DocNav At the Linux command prompt enter docnav Xilinx Design Hubs provide links to documentation organized by design tasks and other topics wh...

Page 28: ...2 Xilinx shall not be liable whether in contract or tort including negligence or under any other theory of liability for any loss or damage of any kind or nature related to arising under or in connect...

Page 29: ...EATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD SAFETY DESIGN CUSTOMER SHALL PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS THOROUGHLY TEST SUCH SYSTEMS FOR SAFET...

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