Table 3: DDR4 PS Interface Pin Map (cont'd)
Pin Number
Signal Name
Description
I/O
AV30
PS_DDR4_1_CK#
DDR4 Clock (N)
O
AW30
PS_DDR4_1_CKE
DDR4 Clock Enable
O
AW29
PS_DDR4_1_CS#
DDR4 Chip Select
O
AR28
PS_DDR4_1_WE#
DDR4 Write Enable
O
AL32
PS_DDR4_1_ALERT#
DDR4 Alert
I
AM33
PS_DDR4_1_RST#
DDR4 Reset
O
Special Functions
FPGA Program Flash
Flash storage for FPGA images on the T2 card is implemented in dual-QSPI mode (8 bits). The
following signals comprise this interface:
• Chip selects:
RF_QSPI_LWR_CS#
and
RF_QSPI_UPR_CS#
• Data:
RF_QSPI_LWR_DQ[3:0]
and
RF_QSPI_UPR_DQ[3:0]
• Clocks:
RF_QSPI_LWR_CLK
and
RF_QSPI_UPR_CLK
Additional details are as follows:
• The dual-QSPI mode flash has been implemented with two 2 Gb SPI NOR flash devices
(Micron MT25QU02GCBB8E12-0AAT).
• The MT25QU02GCBB8E12-0AAT NOR flash devices are automotive grade for thermal
design reasons.
• The flash storage supports a user image and a fallback image.
• The T2 card is shipped with a fallback image that cannot be overwritten (the password is kept
with Xilinx manufacturing).
I2C Bus to Satellite Controller
The I2C bus signals to the Zynq
®
Ult™ RFSoC are
PS_SOC_SCL
and
PS_SOC_SDA
.
These signals are used to support data transfers between the SC and RFSoC in support of the
following functions:
• In-band telemetry: Provides the host access to board power and temperature telemetry data
using PCIe technology.
Chapter 3: Pin Mapping
UG1496 (v1.0) June 15, 2022
T2 Telco Accelerator Card User Guide
18
