DDR4 PL Interface Pins
The following table summarizes the ZU48DR DDR4 PL interface pin map.
Table 2: DDR4 PL Interface Pin Map
Pin Number
Signal Name
Description
I/O
G12
RF_CLK_DDR_N
DDR4 Diff Clock Input (N)
I
G13
RF_CLK_DDR_P
DDR4 Diff Clock Input (P)
I
G9
PL_DDR4_1_A0
DDR4 Address 0
O
G6
PL_DDR4_1_A1
DDR4 Address 1
O
J8
PL_DDR4_1_A2
DDR4 Address 2
O
H7
PL_DDR4_1_A3
DDR4 Address 3
O
F9
PL_DDR4_1_A4
DDR4 Address 4
O
K9
PL_DDR4_1_A5
DDR4 Address 5
O
G7
PL_DDR4_1_A6
DDR4 Address 6
O
J7
PL_DDR4_1_A7
DDR4 Address 7
O
J9
PL_DDR4_1_A8
DDR4 Address 8
O
H6
PL_DDR4_1_A9
DDR4 Address 9
O
E13
PL_DDR4_1_A10
DDR4 Address 10
O
H12
PL_DDR4_1_A11
DDR4 Address 11
O
E12
PL_DDR4_1_A12
DDR4 Address 12
O
G14
PL_DDR4_1_A13
DDR4 Address 13
O
E14
PL_DDR4_1_BA0
DDR4 Bank Address 0
O
H13
PL_DDR4_1_BA1
DDR4 Bank Address 1
O
F14
PL_DDR4_1_BG0
DDR4 Bank Group 0
O
C12
PL_DDR4_1_DM0#
DDR4 Data Mask 0
O
N14
PL_DDR4_1_DM1#
DDR4 Data Mask 1
O
J15
PL_DDR4_1_DM2#
DDR4 Data Mask 2
O
G17
PL_DDR4_1_DM3#
DDR4 Data Mask 3
O
C23
PL_DDR4_1_DM4#
DDR4 Data Mask 4
O
D18
PL_DDR4_1_DM5#
DDR4 Data Mask 5
O
J23
PL_DDR4_1_DM6#
DDR4 Data Mask 6
O
N20
PL_DDR4_1_DM7#
DDR4 Data Mask 7
O
F21
PL_DDR4_1_DM8#
DDR4 Data Mask 8
O
A14
PL_DDR4_1_DQ0
DDR4 Data I/O 0
Bidirectional
A11
PL_DDR4_1_DQ1
DDR4 Data I/O 1
Bidirectional
B14
PL_DDR4_1_DQ2
DDR4 Data I/O 2
Bidirectional
C13
PL_DDR4_1_DQ3
DDR4 Data I/O 3
Bidirectional
B13
PL_DDR4_1_DQ4
DDR4 Data I/O 4
Bidirectional
D13
PL_DDR4_1_DQ5
DDR4 Data I/O 5
Bidirectional
A15
PL_DDR4_1_DQ6
DDR4 Data I/O 6
Bidirectional
Chapter 3: Pin Mapping
UG1496 (v1.0) June 15, 2022
T2 Telco Accelerator Card User Guide
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