AMD XILINX T2 Telco, User Manual

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Table 3: DDR4 PS Interface Pin Map
Pin Number Signal Name Description I/O
AV31 PS_DDR4_1_A0 DDR4 Address 0 O
AW28 PS_DDR4_1_A1 DDR4 Address 1 O
AV28 PS_DDR4_1_A2 DDR4 Address 2 O
AU29 PS_DDR4_1_A3 DDR4 Address 3 O
AW31 PS_DDR4_1_A4 DDR4 Address 4 O
AU28 PS_DDR4_1_A5 DDR4 Address 5 O
AL29 PS_DDR4_1_A6 DDR4 Address 6 O
AM30 PS_DDR4_1_A7 DDR4 Address 7 O
AM29 PS_DDR4_1_A8 DDR4 Address 8 O
AP29 PS_DDR4_1_A9 DDR4 Address 9 O
AT31 PS_DDR4_1_A10 DDR4 Address 10 O
AT32 PS_DDR4_1_A11 DDR4 Address 11 O
AT30 PS_DDR4_1_A12 DDR4 Address 12 O
AU32 PS_DDR4_1_A13 DDR4 Address 13 O
AN30 PS_DDR4_1_BA0 DDR4 Bank Address 0 O
AM32 PS_DDR4_1_BA1 DDR4 Bank Address 1 O
AN32 PS_DDR4_1_BG0 DDR4 Bank Group 0 O
AU23 PS_DDR4_1_DM0# DDR4 Data Mask 0 O
AT27 PS_DDR4_1_DM1# DDR4 Data Mask 1 O
AL24 PS_DDR4_1_DM2# DDR4 Data Mask 2 O
AM27 PS_DDR4_1_DM3# DDR4 Data Mask 3 O
AR38 PS_DDR4_1_DM4# DDR4 Data Mask 4 O
AV22 PS_DDR4_1_DQ0 DDR4 Data I/O 0 Bidirectional
AW24 PS_DDR4_1_DQ1 DDR4 Data I/O 1 Bidirectional
AW23 PS_DDR4_1_DQ2 DDR4 Data I/O 2 Bidirectional
AV25 PS_DDR4_1_DQ3 DDR4 Data I/O 3 Bidirectional
AR23 PS_DDR4_1_DQ4 DDR4 Data I/O 4 Bidirectional
AW25 PS_DDR4_1_DQ5 DDR4 Data I/O 5 Bidirectional
AV23 PS_DDR4_1_DQ6 DDR4 Data I/O 6 Bidirectional
AR24 PS_DDR4_1_DQ7 DDR4 Data I/O 7 Bidirectional
AP26 PS_DDR4_1_DQ8 DDR4 Data I/O 8 Bidirectional
AV27 PS_DDR4_1_DQ9 DDR4 Data I/O 9 Bidirectional
AT25 PS_DDR4_1_DQ10 DDR4 Data I/O 10 Bidirectional
AW26 PS_DDR4_1_DQ11 DDR4 Data I/O 11 Bidirectional
AR27 PS_DDR4_1_DQ12 DDR4 Data I/O 12 Bidirectional
AU27 PS_DDR4_1_DQ13 DDR4 Data I/O 13 Bidirectional
AU25 PS_DDR4_1_DQ14 DDR4 Data I/O 14 Bidirectional
AV26 PS_DDR4_1_DQ15 DDR4 Data I/O 15 Bidirectional
AK24 PS_DDR4_1_DQ16 DDR4 Data I/O 16 Bidirectional
Chapter 3: Pin Mapping
UG1496 (v1.0) June 15, 2022 www.xilinx.com
T2 Telco Accelerator Card User Guide 16
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