Peripheral Control Block
4-7
4.1.4
Power-Save Control Register (PDCON, Offset F0h)
Figure 4-5
Power-Save Control Register (PDCON, offset F0h)
The value of the PDCON register is 0000h at reset.
Bit 15: Enable Power-Save Mode (PSEN)—When set to 1, enables Power-Save mode
and divides the internal operating clock by the value in F2–F0. PSEN is automatically
cleared when an external interrupt, including those generated by on-chip peripheral
devices, occurs. The value of the PSEN bit is not restored by the execution of an IRET
instruction. Software interrupts (INT instruction) and exceptions do not clear the PSEN bit,
and interrupt service routines for these conditions should do so if desired. This bit is 0 after
processor reset.
Bits 14–12: Reserved—Read back as 0.
Bit 11: CLKOUTB Output Frequency (CBF)—When set to 1, CLKOUTB follows the crystal
input (PLL) frequency. When set to 0, CLKOUTB follows the internal processor frequency
(after the clock divisor). Set to 0 on reset.
CLKOUTB can be used as a full-speed clock source in power-save mode.
Bit 10: CLKOUTB Drive Disable (CBD)—When set to 1, CBD three-states the clock output
driver for CLKOUTB. When set to 0, CLKOUTB is driven as an output. Set to 0 on reset.
Bit 9: CLKOUTA Output Frequency (CAF)—When set to 1, CLKOUTA follows the crystal
input (PLL) frequency. When set to 0, CLKOUTA follows the internal processor frequency
(after the clock divisor). Set to 0 on reset.
CLKOUTA can be used as a full-speed clock source in power-save mode.
Bit 8: CLKOUTA Drive Disable (CAD)—When set to 1, CAD three-states the clock output
driver for CLKOUTA. When set to 0, CLKOUTA is driven as an output. Set to 0 on reset.
Bits 7–3: Reserved—Read back as 0.
Bits 2–0: Clock Divisor Select (F2–F0)—Controls the division factor when Power-Save
mode is enabled. Allowable values are as follows:
F2
F1
F0
Divider Factor
0
0
0
Divide by 1 (2
0
)
0
0
1
Divide by 2 (2
1
)
0
1
0
Divide by 4 (2
2
)
0
1
1
Divide by 8 (2
3
)
1
0
0
Divide by 16 (2
4
)
1
0
1
Divide by 32 (2
5
)
1
1
0
Divide by 64 (2
6
)
1
1
1
Divide by 128 (2
7
)
15
7
0
0 0 0
0 0
0 0
0
CBD
CAF
CAD
F1
F0
F2
PSEN
CBF
Summary of Contents for AM186EM
Page 1: ...Am186 EM and Am188 EM Microcontrollers User s Manual...
Page 4: ...iv...
Page 12: ...Table of Contents xii...
Page 62: ...Peripheral Control Block 4 10...
Page 76: ...Chip Select Unit 5 14...
Page 122: ...Timer Control Unit 8 8...
Page 136: ...DMA Controller 9 14...
Page 144: ...Asynchronous Serial Port 10 8...
Page 158: ...Programmable I O Pins 12 6...
Page 186: ...Index I 12...