Interrupt Control Unit
7-20
7.3.7
Interrupt Status Register (INTSTS, Offset 30h)
(Master Mode)
The Interrupt Status (INTSTS) register indicates the interrupt request status of the three
timers.
Figure 7-10
Interrupt Status Register (INTSTS, offset 30h)
Bit 15: DMA Halt (DHLT)—When set to 1, halts any DMA activity. This pin is automatically
set to 1 when non-maskable interrupts occur and is reset when an IRET instruction is
executed. Time-critical software, such as interrupt handlers, can modify this bit directly to
inhibit DMA transfers. Because of the function of this register as an interrupt request register
for the timers, the DHLT bit should not be modified by software when timer interrupts are
enabled.
Bits 14–3: Reserved
Bits 2–0: Timer Interrupt Request (TMR2–TMR0)—When set to 1, these bits indicate
that the corresponding timer has an interrupt request pending. (Note that the timer TMR
bit in the REQST register is the OR of these timer interrupt requests.)
15
7
0
Reserved
TMR2
TMR1
TMR0
DHLT
Summary of Contents for AM186EM
Page 1: ...Am186 EM and Am188 EM Microcontrollers User s Manual...
Page 4: ...iv...
Page 12: ...Table of Contents xii...
Page 62: ...Peripheral Control Block 4 10...
Page 76: ...Chip Select Unit 5 14...
Page 122: ...Timer Control Unit 8 8...
Page 136: ...DMA Controller 9 14...
Page 144: ...Asynchronous Serial Port 10 8...
Page 158: ...Programmable I O Pins 12 6...
Page 186: ...Index I 12...