System Overview
3-3
BHE/ADEN
Bus High Enable, Am186EM Microcontroller Only
(three-state, output, synchronous)
Address Enable, Am186EM Microcontroller Only
(input, internal pullup)
BHE—During a memory access, this pin and the least significant
address bit (AD0 and A0) indicate to the system which bytes of the data
bus (upper, lower, or both) participate in a bus cycle. The BHE/ADEN
and AD0 pins are encoded as shown in the following table.
BHE is asserted during t
1
and remains asserted through t
3
and t
W
. BHE
does not need to be latched. BHE floats during bus hold and reset.
On the Am186EM microcontroller, WLB and WHB implement the
functionality of BHE and AD0 for high and low byte write enables.
BHE/ADEN also signals DRAM refresh cycles when using the
multiplexed address and data (AD) bus. A refresh cycle is indicated
when both BHE/ADEN and AD0 are High. During refresh cycles, the A
bus and the AD bus are not guaranteed to provide the same address
during the address phase of the AD bus cycle. For this reason, the A0
signal cannot be used in place of the AD0 signal to determine refresh
cycles. PSRAM refreshes also provide an additional RFSH signal (see
the MCS3/RFSH pin description).
ADEN—If BHE/ADEN is held High or left floating during power-on reset,
the address portion of the AD bus (AD15–AD0) is enabled or disabled
during LCS and UCS bus cycles based on the DA bit in the Upper
Memory Chip Select (UMCS) and Low Memory Chip Select (LMCS)
registers. If the DA bit is set, the memory address is accessed on the
A19–A0 pins. This mode of operation reduces power consumption.
If BHE/ADEN is held Low on power-on reset, the AD bus always drives
both addresses and data. The pin is sampled one crystal clock cycle
after the rising edge of RES.
See section 5.5.1 and section 5.5.2 for additional information on
enabling and disabling the AD bus during the address phase of a bus
cycle.
CLKOUTA
Clock Output A (output, synchronous)
This pin supplies the internal clock to the system. Depending on the
value of the Power-Save Control (PDCON) register, CLKOUTA
operates at either the crystal input frequency (X1), the power-save
frequency, or is three-stated. CLKOUTA remains active during reset
and bus hold conditions.
BHE
AD0
Type of Bus Cycle
0
0
Word Transfer
0
1
High Byte Transfer (Bits 15–8)
1
0
Low Byte Transfer (Bits 7–0)
1
1
Refresh
Summary of Contents for AM186EM
Page 1: ...Am186 EM and Am188 EM Microcontrollers User s Manual...
Page 4: ...iv...
Page 12: ...Table of Contents xii...
Page 62: ...Peripheral Control Block 4 10...
Page 76: ...Chip Select Unit 5 14...
Page 122: ...Timer Control Unit 8 8...
Page 136: ...DMA Controller 9 14...
Page 144: ...Asynchronous Serial Port 10 8...
Page 158: ...Programmable I O Pins 12 6...
Page 186: ...Index I 12...